Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	28079290	15603	0	0
attest_sw_binding_0_rd_A	28079290	2757	0	0
attest_sw_binding_1_rd_A	28079290	2911	0	0
attest_sw_binding_2_rd_A	28079290	2687	0	0
attest_sw_binding_3_rd_A	28079290	2742	0	0
attest_sw_binding_4_rd_A	28079290	2910	0	0
attest_sw_binding_5_rd_A	28079290	2655	0	0
attest_sw_binding_6_rd_A	28079290	2401	0	0
attest_sw_binding_7_rd_A	28079290	2556	0	0
intr_enable_rd_A	28079290	3210	0	0
key_version_rd_A	28079290	2709	0	0
max_creator_key_ver_regwen_rd_A	28079290	2860	0	0
max_owner_int_key_ver_regwen_rd_A	28079290	2697	0	0
max_owner_key_ver_regwen_rd_A	28079290	2831	0	0
reseed_interval_regwen_rd_A	28079290	2897	0	0
salt_0_rd_A	28079290	2805	0	0
salt_1_rd_A	28079290	2672	0	0
salt_2_rd_A	28079290	2703	0	0
salt_3_rd_A	28079290	2726	0	0
salt_4_rd_A	28079290	2775	0	0
salt_5_rd_A	28079290	2594	0	0
salt_6_rd_A	28079290	2630	0	0
salt_7_rd_A	28079290	2633	0	0
sealing_sw_binding_0_rd_A	28079290	2883	0	0
sealing_sw_binding_1_rd_A	28079290	2595	0	0
sealing_sw_binding_2_rd_A	28079290	2826	0	0
sealing_sw_binding_3_rd_A	28079290	2725	0	0
sealing_sw_binding_4_rd_A	28079290	2858	0	0
sealing_sw_binding_5_rd_A	28079290	2698	0	0
sealing_sw_binding_6_rd_A	28079290	2675	0	0
sealing_sw_binding_7_rd_A	28079290	2838	0	0
sideload_clear_rd_A	28079290	2681	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	15603	0	0
T4	96148	0	0	0
T6	0	172	0	0
T9	61911	0	0	0
T29	35899	758	0	0
T42	3890	0	0	0
T52	6421	0	0	0
T54	0	39	0	0
T55	5918	0	0	0
T64	0	1368	0	0
T65	0	270	0	0
T70	0	684	0	0
T74	0	85	0	0
T83	6976	0	0	0
T84	10147	0	0	0
T85	9265	0	0	0
T86	17383	0	0	0
T113	0	38	0	0
T115	0	219	0	0
T136	0	368	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2757	0	0
T6	51059	0	0	0
T54	21480	23	0	0
T74	0	82	0	0
T90	1592	0	0	0
T113	0	46	0	0
T115	0	63	0	0
T134	0	45	0	0
T165	0	18	0	0
T166	0	18	0	0
T167	0	32	0	0
T168	0	25	0	0
T169	0	23	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2911	0	0
T6	51059	0	0	0
T54	21480	19	0	0
T74	0	68	0	0
T90	1592	0	0	0
T113	0	36	0	0
T115	0	72	0	0
T134	0	69	0	0
T165	0	20	0	0
T166	0	45	0	0
T167	0	36	0	0
T168	0	47	0	0
T169	0	23	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2687	0	0
T6	51059	0	0	0
T54	21480	42	0	0
T74	0	63	0	0
T90	1592	0	0	0
T113	0	15	0	0
T115	0	81	0	0
T134	0	32	0	0
T165	0	11	0	0
T166	0	28	0	0
T167	0	24	0	0
T168	0	27	0	0
T169	0	13	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2742	0	0
T6	51059	0	0	0
T54	21480	26	0	0
T74	0	48	0	0
T90	1592	0	0	0
T113	0	27	0	0
T115	0	71	0	0
T134	0	33	0	0
T165	0	12	0	0
T166	0	38	0	0
T167	0	18	0	0
T168	0	24	0	0
T169	0	17	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2910	0	0
T6	51059	0	0	0
T54	21480	24	0	0
T74	0	74	0	0
T90	1592	0	0	0
T113	0	24	0	0
T115	0	51	0	0
T134	0	41	0	0
T165	0	12	0	0
T166	0	25	0	0
T167	0	22	0	0
T168	0	25	0	0
T169	0	7	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2655	0	0
T6	51059	0	0	0
T54	21480	22	0	0
T74	0	36	0	0
T90	1592	0	0	0
T113	0	34	0	0
T115	0	68	0	0
T134	0	63	0	0
T165	0	8	0	0
T166	0	21	0	0
T167	0	14	0	0
T168	0	14	0	0
T169	0	8	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2401	0	0
T6	51059	0	0	0
T54	21480	18	0	0
T74	0	46	0	0
T90	1592	0	0	0
T113	0	10	0	0
T115	0	83	0	0
T134	0	28	0	0
T165	0	12	0	0
T166	0	23	0	0
T167	0	15	0	0
T168	0	22	0	0
T169	0	17	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2556	0	0
T6	51059	0	0	0
T54	21480	23	0	0
T74	0	55	0	0
T90	1592	0	0	0
T113	0	29	0	0
T115	0	47	0	0
T134	0	65	0	0
T165	0	10	0	0
T166	0	28	0	0
T167	0	30	0	0
T168	0	32	0	0
T169	0	6	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	3210	0	0
T6	51059	0	0	0
T54	21480	36	0	0
T74	0	67	0	0
T90	1592	0	0	0
T113	0	55	0	0
T115	0	84	0	0
T165	0	12	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0
T177	0	37	0	0
T178	0	15	0	0
T179	0	33	0	0
T180	0	65	0	0
T181	0	23	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2709	0	0
T6	51059	0	0	0
T54	21480	11	0	0
T74	0	51	0	0
T90	1592	0	0	0
T113	0	12	0	0
T115	0	76	0	0
T134	0	50	0	0
T165	0	13	0	0
T166	0	68	0	0
T167	0	15	0	0
T168	0	54	0	0
T169	0	12	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2860	0	0
T6	51059	0	0	0
T54	21480	26	0	0
T74	0	74	0	0
T90	1592	0	0	0
T113	0	32	0	0
T115	0	78	0	0
T134	0	49	0	0
T165	0	8	0	0
T166	0	39	0	0
T167	0	29	0	0
T168	0	38	0	0
T169	0	13	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2697	0	0
T6	51059	0	0	0
T54	21480	40	0	0
T74	0	75	0	0
T90	1592	0	0	0
T113	0	30	0	0
T115	0	60	0	0
T134	0	42	0	0
T165	0	14	0	0
T166	0	39	0	0
T167	0	28	0	0
T168	0	29	0	0
T169	0	10	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2831	0	0
T6	51059	0	0	0
T54	21480	19	0	0
T74	0	73	0	0
T90	1592	0	0	0
T113	0	26	0	0
T115	0	66	0	0
T134	0	23	0	0
T165	0	15	0	0
T166	0	33	0	0
T167	0	38	0	0
T168	0	29	0	0
T169	0	21	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2897	0	0
T6	51059	0	0	0
T54	21480	10	0	0
T74	0	45	0	0
T90	1592	0	0	0
T113	0	21	0	0
T115	0	61	0	0
T134	0	34	0	0
T165	0	7	0	0
T166	0	49	0	0
T167	0	29	0	0
T168	0	28	0	0
T169	0	21	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2805	0	0
T6	51059	0	0	0
T54	21480	41	0	0
T74	0	69	0	0
T90	1592	0	0	0
T113	0	25	0	0
T115	0	74	0	0
T134	0	57	0	0
T165	0	19	0	0
T166	0	27	0	0
T167	0	26	0	0
T168	0	25	0	0
T169	0	20	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2672	0	0
T6	51059	0	0	0
T54	21480	45	0	0
T74	0	52	0	0
T90	1592	0	0	0
T113	0	18	0	0
T115	0	44	0	0
T134	0	44	0	0
T165	0	6	0	0
T166	0	22	0	0
T167	0	26	0	0
T168	0	20	0	0
T169	0	4	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2703	0	0
T6	51059	0	0	0
T54	21480	25	0	0
T74	0	53	0	0
T90	1592	0	0	0
T113	0	26	0	0
T115	0	65	0	0
T134	0	49	0	0
T165	0	27	0	0
T166	0	29	0	0
T167	0	29	0	0
T168	0	29	0	0
T169	0	10	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2726	0	0
T6	51059	0	0	0
T54	21480	34	0	0
T74	0	84	0	0
T90	1592	0	0	0
T113	0	21	0	0
T115	0	57	0	0
T134	0	35	0	0
T165	0	31	0	0
T166	0	22	0	0
T167	0	28	0	0
T168	0	26	0	0
T169	0	5	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2775	0	0
T6	51059	0	0	0
T54	21480	23	0	0
T74	0	59	0	0
T90	1592	0	0	0
T113	0	21	0	0
T115	0	66	0	0
T134	0	27	0	0
T165	0	17	0	0
T166	0	32	0	0
T167	0	37	0	0
T168	0	46	0	0
T169	0	24	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2594	0	0
T6	51059	0	0	0
T54	21480	27	0	0
T74	0	58	0	0
T90	1592	0	0	0
T113	0	10	0	0
T115	0	58	0	0
T165	0	12	0	0
T166	0	18	0	0
T167	0	15	0	0
T168	0	17	0	0
T169	0	22	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0
T182	0	1	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2630	0	0
T6	51059	0	0	0
T54	21480	34	0	0
T74	0	62	0	0
T90	1592	0	0	0
T113	0	29	0	0
T115	0	46	0	0
T134	0	54	0	0
T165	0	8	0	0
T166	0	35	0	0
T167	0	45	0	0
T168	0	38	0	0
T169	0	6	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2633	0	0
T6	51059	0	0	0
T54	21480	21	0	0
T74	0	79	0	0
T90	1592	0	0	0
T113	0	28	0	0
T115	0	56	0	0
T134	0	35	0	0
T165	0	9	0	0
T166	0	21	0	0
T167	0	24	0	0
T168	0	18	0	0
T169	0	26	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2883	0	0
T6	51059	0	0	0
T54	21480	16	0	0
T74	0	61	0	0
T90	1592	0	0	0
T113	0	29	0	0
T115	0	70	0	0
T165	0	5	0	0
T166	0	27	0	0
T167	0	48	0	0
T168	0	35	0	0
T169	0	21	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0
T183	0	8	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2595	0	0
T6	51059	0	0	0
T54	21480	31	0	0
T74	0	82	0	0
T90	1592	0	0	0
T113	0	27	0	0
T115	0	49	0	0
T134	0	38	0	0
T165	0	37	0	0
T166	0	21	0	0
T167	0	17	0	0
T168	0	49	0	0
T169	0	15	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2826	0	0
T6	51059	0	0	0
T54	21480	27	0	0
T74	0	51	0	0
T90	1592	0	0	0
T113	0	21	0	0
T115	0	72	0	0
T134	0	65	0	0
T165	0	26	0	0
T166	0	58	0	0
T167	0	27	0	0
T168	0	25	0	0
T169	0	8	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2725	0	0
T6	51059	0	0	0
T54	21480	22	0	0
T74	0	87	0	0
T90	1592	0	0	0
T113	0	22	0	0
T115	0	58	0	0
T134	0	33	0	0
T165	0	28	0	0
T166	0	50	0	0
T167	0	35	0	0
T168	0	12	0	0
T169	0	23	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2858	0	0
T6	51059	0	0	0
T54	21480	21	0	0
T74	0	68	0	0
T90	1592	0	0	0
T113	0	43	0	0
T115	0	80	0	0
T134	0	45	0	0
T165	0	14	0	0
T166	0	31	0	0
T167	0	35	0	0
T168	0	49	0	0
T169	0	17	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2698	0	0
T6	51059	0	0	0
T54	21480	32	0	0
T74	0	58	0	0
T90	1592	0	0	0
T113	0	35	0	0
T115	0	64	0	0
T134	0	41	0	0
T165	0	22	0	0
T166	0	48	0	0
T167	0	16	0	0
T168	0	30	0	0
T169	0	21	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2675	0	0
T6	51059	0	0	0
T54	21480	39	0	0
T74	0	87	0	0
T90	1592	0	0	0
T113	0	27	0	0
T115	0	69	0	0
T134	0	70	0	0
T165	0	22	0	0
T166	0	34	0	0
T167	0	33	0	0
T168	0	52	0	0
T169	0	11	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2838	0	0
T6	51059	0	0	0
T54	21480	33	0	0
T74	0	75	0	0
T90	1592	0	0	0
T113	0	30	0	0
T115	0	86	0	0
T134	0	24	0	0
T165	0	24	0	0
T166	0	15	0	0
T167	0	32	0	0
T168	0	31	0	0
T169	0	2	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28079290	2681	0	0
T6	51059	0	0	0
T54	21480	34	0	0
T74	0	71	0	0
T90	1592	0	0	0
T113	0	34	0	0
T115	0	90	0	0
T134	0	42	0	0
T165	0	17	0	0
T166	0	35	0	0
T167	0	22	0	0
T168	0	22	0	0
T169	0	9	0	0
T170	12170	0	0	0
T171	10538	0	0	0
T172	9250	0	0	0
T173	6695	0	0	0
T174	917	0	0	0
T175	50039	0	0	0
T176	8650	0	0	0