Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3212217	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

592229

1

T1

488

T2

178

T3

264

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3404536	1			T1	481		T2	5242		T3	832
values[0x0]	198760	1			T1	213		T2	59		T3	136
values[0x1]	201150	1			T1	207		T2	49		T3	107

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2197695	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1606751

1

T1

572

T2

1826

T3

495

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11299	1			T2	13		T3	2		T4	115
valid_sources[0x01]	12191	1			T1	7		T2	32		T3	9
valid_sources[0x02]	12344	1			T1	3		T2	19		T3	4
valid_sources[0x03]	26058	1			T2	16		T3	6		T4	145
valid_sources[0x04]	10627	1			T1	1		T2	19		T3	3
valid_sources[0x05]	19068	1			T1	7		T2	16		T4	134
valid_sources[0x06]	11709	1			T2	13		T3	5		T4	107
valid_sources[0x07]	20101	1			T2	24		T3	3		T4	105
valid_sources[0x08]	12143	1			T1	7		T2	22		T3	4
valid_sources[0x09]	11346	1			T2	27		T3	4		T4	145
valid_sources[0x0a]	11939	1			T1	18		T2	21		T3	5
valid_sources[0x0b]	14809	1			T2	17		T3	6		T4	138
valid_sources[0x0c]	18629	1			T2	22		T3	3		T4	86
valid_sources[0x0d]	12034	1			T2	23		T3	3		T4	102
valid_sources[0x0e]	13057	1			T1	4		T2	16		T3	5
valid_sources[0x0f]	11330	1			T1	5		T2	22		T3	2
valid_sources[0x10]	10886	1			T2	10		T3	4		T4	112
valid_sources[0x11]	18027	1			T2	23		T3	6		T4	94
valid_sources[0x12]	12448	1			T1	6		T2	37		T3	5
valid_sources[0x13]	11648	1			T1	5		T2	21		T3	4
valid_sources[0x14]	19840	1			T2	25		T3	2		T4	107
valid_sources[0x15]	12822	1			T1	14		T2	19		T3	7
valid_sources[0x16]	11468	1			T2	22		T3	4		T4	142
valid_sources[0x17]	12487	1			T1	11		T2	15		T3	5
valid_sources[0x18]	11128	1			T2	25		T3	8		T4	117
valid_sources[0x19]	11836	1			T1	20		T2	9		T3	5
valid_sources[0x1a]	13379	1			T2	32		T3	2		T4	90
valid_sources[0x1b]	10961	1			T1	4		T2	24		T3	5
valid_sources[0x1c]	17851	1			T2	34		T4	144		T12	21
valid_sources[0x1d]	10841	1			T2	19		T3	3		T4	116
valid_sources[0x1e]	12247	1			T2	14		T3	3		T4	134
valid_sources[0x1f]	12560	1			T1	7		T2	22		T3	1
valid_sources[0x20]	12269	1			T1	1		T2	28		T3	6
valid_sources[0x21]	13545	1			T2	16		T4	86		T5	33
valid_sources[0x22]	11356	1			T2	26		T3	7		T4	128
valid_sources[0x23]	11315	1			T1	12		T2	24		T3	5
valid_sources[0x24]	14236	1			T2	17		T3	2		T4	107
valid_sources[0x25]	14061	1			T1	21		T2	26		T3	6
valid_sources[0x26]	12034	1			T2	29		T3	4		T4	96
valid_sources[0x27]	28035	1			T1	5		T2	19		T3	2
valid_sources[0x28]	11171	1			T2	24		T3	4		T4	89
valid_sources[0x29]	44283	1			T1	3		T2	19		T3	5
valid_sources[0x2a]	12385	1			T1	27		T2	19		T3	4
valid_sources[0x2b]	12201	1			T1	3		T2	16		T3	4
valid_sources[0x2c]	11301	1			T2	33		T3	5		T4	133
valid_sources[0x2d]	12078	1			T2	24		T3	2		T4	119
valid_sources[0x2e]	17796	1			T1	9		T2	20		T3	5
valid_sources[0x2f]	19951	1			T2	18		T3	4		T4	123
valid_sources[0x30]	12721	1			T2	22		T3	2		T4	93
valid_sources[0x31]	11995	1			T2	19		T3	1		T4	88
valid_sources[0x32]	12012	1			T1	3		T2	18		T3	2
valid_sources[0x33]	11530	1			T2	28		T3	1		T4	81
valid_sources[0x34]	15897	1			T1	23		T2	32		T3	4
valid_sources[0x35]	14057	1			T1	12		T2	19		T3	4
valid_sources[0x36]	11200	1			T2	25		T3	6		T4	133
valid_sources[0x37]	12973	1			T1	12		T2	15		T3	4
valid_sources[0x38]	24550	1			T1	2		T2	27		T3	3
valid_sources[0x39]	11692	1			T2	17		T3	7		T4	127
valid_sources[0x3a]	11149	1			T1	1		T2	18		T4	103
valid_sources[0x3b]	18403	1			T2	11		T3	3		T4	147
valid_sources[0x3c]	11193	1			T2	26		T4	89		T5	30
valid_sources[0x3d]	12863	1			T2	16		T3	2		T4	140
valid_sources[0x3e]	14127	1			T2	29		T3	5		T4	120
valid_sources[0x3f]	12511	1			T2	11		T3	8		T4	84
valid_sources[0x40]	14391	1			T2	16		T3	8		T4	120
valid_sources[0x41]	21690	1			T2	19		T3	3		T4	83
valid_sources[0x42]	11692	1			T2	20		T3	7		T4	107
valid_sources[0x43]	17393	1			T2	23		T3	2		T4	88
valid_sources[0x44]	16920	1			T2	23		T3	2		T4	117
valid_sources[0x45]	12184	1			T1	10		T2	22		T3	7
valid_sources[0x46]	23784	1			T1	1		T2	15		T3	7
valid_sources[0x47]	14881	1			T1	2		T2	16		T3	5
valid_sources[0x48]	11316	1			T1	9		T2	15		T3	2
valid_sources[0x49]	37298	1			T1	5		T2	27		T3	3
valid_sources[0x4a]	11783	1			T2	17		T3	2		T4	78
valid_sources[0x4b]	12441	1			T2	23		T3	4		T4	96
valid_sources[0x4c]	13185	1			T2	17		T3	6		T4	76
valid_sources[0x4d]	11158	1			T2	20		T3	2		T4	71
valid_sources[0x4e]	13150	1			T1	6		T2	18		T3	6
valid_sources[0x4f]	11178	1			T2	22		T3	1		T4	115
valid_sources[0x50]	11760	1			T2	28		T3	3		T4	99
valid_sources[0x51]	11820	1			T2	37		T3	9		T4	77
valid_sources[0x52]	12256	1			T2	12		T3	3		T4	150
valid_sources[0x53]	13734	1			T2	24		T3	8		T4	115
valid_sources[0x54]	11891	1			T2	38		T3	5		T4	134
valid_sources[0x55]	11855	1			T2	21		T3	6		T4	125
valid_sources[0x56]	11110	1			T2	19		T3	4		T4	76
valid_sources[0x57]	12234	1			T2	29		T3	2		T4	141
valid_sources[0x58]	11829	1			T2	21		T3	2		T4	96
valid_sources[0x59]	18801	1			T2	33		T3	4		T4	134
valid_sources[0x5a]	12281	1			T2	26		T3	6		T4	89
valid_sources[0x5b]	13554	1			T1	15		T2	35		T3	3
valid_sources[0x5c]	25948	1			T2	20		T3	2		T4	103
valid_sources[0x5d]	13186	1			T1	3		T2	19		T3	6
valid_sources[0x5e]	14667	1			T1	1		T2	14		T3	3
valid_sources[0x5f]	28410	1			T2	21		T3	2		T4	141
valid_sources[0x60]	13742	1			T1	4		T2	23		T3	5
valid_sources[0x61]	11438	1			T2	22		T3	10		T4	107
valid_sources[0x62]	11280	1			T1	6		T2	24		T3	3
valid_sources[0x63]	11112	1			T1	4		T2	19		T3	4
valid_sources[0x64]	11035	1			T1	6		T2	28		T3	2
valid_sources[0x65]	16509	1			T2	23		T3	3		T4	94
valid_sources[0x66]	31176	1			T2	19		T3	2		T4	80
valid_sources[0x67]	20357	1			T2	30		T3	1		T4	92
valid_sources[0x68]	13067	1			T2	38		T3	3		T4	86
valid_sources[0x69]	15780	1			T2	12		T3	5		T4	81
valid_sources[0x6a]	13374	1			T1	14		T2	14		T3	7
valid_sources[0x6b]	11882	1			T1	9		T2	19		T3	9
valid_sources[0x6c]	11982	1			T2	26		T3	6		T4	121
valid_sources[0x6d]	11008	1			T1	5		T2	29		T3	6
valid_sources[0x6e]	11588	1			T2	29		T3	2		T4	87
valid_sources[0x6f]	12099	1			T1	17		T2	18		T3	3
valid_sources[0x70]	15333	1			T2	17		T3	4		T4	124
valid_sources[0x71]	11627	1			T2	18		T3	5		T4	65
valid_sources[0x72]	14274	1			T1	3		T2	28		T3	9
valid_sources[0x73]	11614	1			T2	22		T3	6		T4	126
valid_sources[0x74]	12753	1			T2	25		T3	5		T4	71
valid_sources[0x75]	11919	1			T1	2		T2	16		T3	3
valid_sources[0x76]	11730	1			T1	2		T2	13		T3	5
valid_sources[0x77]	12077	1			T1	13		T2	23		T3	2
valid_sources[0x78]	12186	1			T2	25		T3	5		T4	105
valid_sources[0x79]	18586	1			T2	23		T3	3		T4	137
valid_sources[0x7a]	11717	1			T2	21		T3	3		T4	97
valid_sources[0x7b]	16019	1			T2	23		T3	2		T4	112
valid_sources[0x7c]	11243	1			T2	19		T3	4		T4	106
valid_sources[0x7d]	11710	1			T2	34		T3	5		T4	85
valid_sources[0x7e]	12883	1			T2	20		T3	2		T4	122
valid_sources[0x7f]	12420	1			T2	9		T3	4		T4	153
valid_sources[0x80]	11416	1			T2	15		T3	9		T4	96

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

319837

1

T1

210

T2

138

T3

68

values[0x0]

all_enables

biggest_size

143442

1

T1

153

T2

29

T3

110

values[0x1]

all_enables

biggest_size

128950

1

T1

125

T2

11

T3

86