Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
21955557 |
21792773 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21955557 |
21792773 |
0 |
0 |
T1 |
2939 |
2845 |
0 |
0 |
T2 |
44776 |
44717 |
0 |
0 |
T3 |
13384 |
13300 |
0 |
0 |
T4 |
82446 |
82339 |
0 |
0 |
T5 |
27675 |
27594 |
0 |
0 |
T9 |
76445 |
62785 |
0 |
0 |
T12 |
60527 |
60433 |
0 |
0 |
T13 |
10094 |
10040 |
0 |
0 |
T14 |
7411 |
7330 |
0 |
0 |
T15 |
12191 |
12110 |
0 |
0 |