Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3419093	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

616466

1

T1

44

T2

125

T3

1125

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3613781	1			T1	128		T2	374		T3	21693
values[0x0]	209187	1			T1	15		T2	35		T3	406
values[0x1]	212591	1			T1	11		T2	50		T3	404

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2337153	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1698406

1

T1

68

T2

221

T3

8153

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19615	1			T3	97		T4	28		T16	1
valid_sources[0x01]	18479	1			T1	1		T3	85		T4	12
valid_sources[0x02]	11374	1			T3	75		T4	5		T14	1
valid_sources[0x03]	10656	1			T1	1		T3	64		T4	14
valid_sources[0x04]	10912	1			T1	1		T3	94		T4	7
valid_sources[0x05]	13183	1			T1	1		T3	111		T4	1
valid_sources[0x06]	11523	1			T3	74		T4	10		T14	4
valid_sources[0x07]	25875	1			T3	53		T4	16		T14	8
valid_sources[0x08]	13710	1			T3	85		T4	13		T14	5
valid_sources[0x09]	11095	1			T3	102		T4	12		T14	21
valid_sources[0x0a]	12420	1			T3	79		T4	19		T14	3
valid_sources[0x0b]	10623	1			T3	72		T4	17		T14	6
valid_sources[0x0c]	100949	1			T3	53		T4	10		T14	2
valid_sources[0x0d]	14345	1			T3	72		T4	3		T14	3
valid_sources[0x0e]	10610	1			T1	4		T3	71		T4	1
valid_sources[0x0f]	10921	1			T1	1		T3	76		T4	11
valid_sources[0x10]	10866	1			T1	1		T3	85		T4	3
valid_sources[0x11]	11722	1			T3	72		T4	5		T14	8
valid_sources[0x12]	10621	1			T3	70		T4	14		T14	2
valid_sources[0x13]	12030	1			T1	1		T3	68		T4	18
valid_sources[0x14]	11351	1			T3	89		T4	13		T14	10
valid_sources[0x15]	12196	1			T3	122		T4	6		T14	3
valid_sources[0x16]	11122	1			T3	104		T4	10		T14	7
valid_sources[0x17]	11228	1			T3	113		T4	15		T14	1
valid_sources[0x18]	11316	1			T1	2		T3	88		T4	15
valid_sources[0x19]	10682	1			T3	109		T4	16		T14	3
valid_sources[0x1a]	11203	1			T1	2		T3	93		T4	9
valid_sources[0x1b]	11596	1			T1	1		T3	104		T4	17
valid_sources[0x1c]	10537	1			T3	99		T4	16		T14	1
valid_sources[0x1d]	11373	1			T3	74		T4	4		T14	6
valid_sources[0x1e]	20109	1			T1	1		T3	88		T4	20
valid_sources[0x1f]	12520	1			T3	97		T4	11		T14	1
valid_sources[0x20]	36395	1			T3	109		T4	15		T14	1
valid_sources[0x21]	11119	1			T3	83		T4	4		T14	7
valid_sources[0x22]	15723	1			T3	50		T4	14		T14	1
valid_sources[0x23]	11323	1			T3	96		T4	27		T14	4
valid_sources[0x24]	12578	1			T3	101		T4	27		T14	6
valid_sources[0x25]	10886	1			T1	2		T3	76		T4	6
valid_sources[0x26]	12339	1			T3	94		T4	10		T14	10
valid_sources[0x27]	13677	1			T3	83		T4	8		T14	2
valid_sources[0x28]	11335	1			T3	63		T4	11		T15	11
valid_sources[0x29]	11915	1			T1	3		T3	111		T4	11
valid_sources[0x2a]	13301	1			T3	83		T4	17		T14	5
valid_sources[0x2b]	10962	1			T3	98		T4	11		T14	1
valid_sources[0x2c]	11007	1			T1	2		T3	94		T4	5
valid_sources[0x2d]	12145	1			T3	85		T4	21		T15	5
valid_sources[0x2e]	11379	1			T3	74		T4	6		T14	4
valid_sources[0x2f]	12308	1			T1	1		T3	61		T4	5
valid_sources[0x30]	10317	1			T1	1		T3	56		T4	9
valid_sources[0x31]	11418	1			T3	82		T4	14		T15	12
valid_sources[0x32]	11777	1			T1	1		T3	100		T4	4
valid_sources[0x33]	10713	1			T1	1		T3	86		T4	2
valid_sources[0x34]	11243	1			T1	1		T3	66		T4	27
valid_sources[0x35]	11392	1			T1	1		T3	95		T4	15
valid_sources[0x36]	10887	1			T3	75		T4	8		T14	2
valid_sources[0x37]	13915	1			T3	54		T4	2		T14	5
valid_sources[0x38]	11485	1			T1	1		T3	93		T4	4
valid_sources[0x39]	11378	1			T1	1		T3	61		T4	16
valid_sources[0x3a]	11028	1			T3	59		T4	16		T14	1
valid_sources[0x3b]	12863	1			T3	76		T4	12		T14	1
valid_sources[0x3c]	11497	1			T1	3		T3	75		T4	13
valid_sources[0x3d]	10724	1			T3	58		T4	5		T15	5
valid_sources[0x3e]	10449	1			T3	110		T4	8		T14	3
valid_sources[0x3f]	10717	1			T3	72		T4	10		T14	7
valid_sources[0x40]	12075	1			T3	114		T4	9		T14	1
valid_sources[0x41]	12381	1			T1	2		T3	70		T4	13
valid_sources[0x42]	13124	1			T1	2		T3	107		T4	4
valid_sources[0x43]	36379	1			T3	85		T4	12		T14	2
valid_sources[0x44]	11603	1			T3	126		T4	11		T14	3
valid_sources[0x45]	14272	1			T1	1		T3	98		T4	23
valid_sources[0x46]	14437	1			T1	2		T3	88		T4	9
valid_sources[0x47]	11220	1			T1	1		T3	124		T4	18
valid_sources[0x48]	11148	1			T3	121		T4	2		T14	1
valid_sources[0x49]	12117	1			T1	1		T3	80		T4	6
valid_sources[0x4a]	11562	1			T3	77		T4	9		T14	4
valid_sources[0x4b]	10957	1			T1	2		T3	132		T4	8
valid_sources[0x4c]	10810	1			T3	90		T4	17		T14	4
valid_sources[0x4d]	11576	1			T1	1		T3	94		T4	25
valid_sources[0x4e]	16916	1			T3	82		T4	6		T14	7
valid_sources[0x4f]	28758	1			T3	87		T4	7		T15	3
valid_sources[0x50]	11612	1			T1	2		T3	67		T4	12
valid_sources[0x51]	11131	1			T3	73		T4	16		T14	2
valid_sources[0x52]	14351	1			T1	3		T3	108		T4	16
valid_sources[0x53]	12750	1			T1	1		T2	459		T3	82
valid_sources[0x54]	16347	1			T3	73		T4	2		T14	3
valid_sources[0x55]	11294	1			T3	76		T4	11		T14	10
valid_sources[0x56]	10779	1			T1	1		T3	95		T4	8
valid_sources[0x57]	10877	1			T1	1		T3	98		T4	6
valid_sources[0x58]	11350	1			T1	1		T3	69		T4	15
valid_sources[0x59]	11261	1			T3	90		T4	9		T15	22
valid_sources[0x5a]	12595	1			T1	1		T3	74		T4	22
valid_sources[0x5b]	13961	1			T1	2		T3	94		T4	2
valid_sources[0x5c]	13139	1			T1	1		T3	51		T4	10
valid_sources[0x5d]	10766	1			T3	60		T4	5		T14	1
valid_sources[0x5e]	42768	1			T3	93		T4	11		T14	3
valid_sources[0x5f]	10855	1			T3	82		T4	14		T14	1
valid_sources[0x60]	13185	1			T1	6		T3	112		T4	20
valid_sources[0x61]	10823	1			T3	95		T4	5		T14	5
valid_sources[0x62]	14807	1			T3	74		T4	10		T14	2
valid_sources[0x63]	11310	1			T1	2		T3	85		T4	16
valid_sources[0x64]	14832	1			T1	1		T3	62		T4	4
valid_sources[0x65]	20751	1			T1	1		T3	82		T4	6
valid_sources[0x66]	16776	1			T3	83		T4	9		T14	7
valid_sources[0x67]	11552	1			T1	1		T3	95		T4	11
valid_sources[0x68]	11671	1			T3	107		T4	11		T14	2
valid_sources[0x69]	10577	1			T1	1		T3	65		T4	10
valid_sources[0x6a]	10775	1			T1	3		T3	97		T4	21
valid_sources[0x6b]	10601	1			T1	1		T3	107		T4	5
valid_sources[0x6c]	10519	1			T3	111		T4	17		T14	3
valid_sources[0x6d]	24166	1			T1	1		T3	65		T4	2
valid_sources[0x6e]	10614	1			T1	1		T3	97		T4	21
valid_sources[0x6f]	10654	1			T1	1		T3	82		T4	10
valid_sources[0x70]	11054	1			T3	99		T4	7		T15	2
valid_sources[0x71]	12173	1			T3	89		T4	34		T14	3
valid_sources[0x72]	23986	1			T3	135		T4	21		T14	2
valid_sources[0x73]	12792	1			T3	106		T4	11		T14	2
valid_sources[0x74]	11572	1			T1	1		T3	68		T4	7
valid_sources[0x75]	11439	1			T1	1		T3	82		T4	5
valid_sources[0x76]	10655	1			T1	1		T3	107		T4	4
valid_sources[0x77]	10469	1			T1	1		T3	97		T4	11
valid_sources[0x78]	10927	1			T3	68		T4	10		T14	3
valid_sources[0x79]	10633	1			T1	2		T3	58		T4	5
valid_sources[0x7a]	14181	1			T3	99		T4	6		T14	4
valid_sources[0x7b]	13576	1			T3	132		T4	14		T14	7
valid_sources[0x7c]	12263	1			T1	4		T3	113		T14	1
valid_sources[0x7d]	12245	1			T3	78		T4	7		T14	4
valid_sources[0x7e]	15138	1			T3	112		T4	6		T15	15
valid_sources[0x7f]	10216	1			T1	1		T3	67		T4	19
valid_sources[0x80]	10862	1			T1	6		T3	81		T4	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

329858

1

T1

36

T2

102

T3

674

values[0x0]

all_enables

biggest_size

150835

1

T1

5

T2

14

T3

244

values[0x1]

all_enables

biggest_size

135773

1

T1

3

T2

9

T3

207