Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
27282294 |
27119002 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27282294 |
27119002 |
0 |
0 |
T1 |
4903 |
4784 |
0 |
0 |
T2 |
4596 |
4539 |
0 |
0 |
T3 |
106943 |
106546 |
0 |
0 |
T4 |
11916 |
11832 |
0 |
0 |
T13 |
6122 |
5988 |
0 |
0 |
T14 |
9636 |
9548 |
0 |
0 |
T15 |
20838 |
20631 |
0 |
0 |
T16 |
5868 |
5668 |
0 |
0 |
T17 |
1328 |
1233 |
0 |
0 |
T18 |
76166 |
75577 |
0 |
0 |