Unified Coverage Report :: Module :: keymgr

Module : keymgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.94	96.00	97.81	99.96		95.92	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	97.94	96.00	97.81	99.96		95.92	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.94	96.00	97.81	99.96		95.92	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.80	99.04	97.68	98.65	100.00	99.02	98.41

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sw_assigns[0].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[0].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[1].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[1].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[2].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[2].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[3].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[3].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[4].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[4].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[5].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[5].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[6].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[6].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[7].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[7].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share1_de	100.00	100.00
keymgr_csr_assert	100.00						100.00
tlul_assert_device	99.30	100.00				100.00	97.90
u_cfgen	98.15	100.00	94.44			100.00
u_checks	100.00	100.00					100.00
u_ctrl	97.22	99.71	95.29	95.57	100.00	98.65	94.12
u_fault_alert	100.00			100.00
u_intr_op_done	100.00	100.00	100.00			100.00	100.00
u_kmac_if	96.70	100.00	87.01	100.00	100.00	93.18	100.00
u_lc_keymgr_en_sync	100.00	100.00				100.00	100.00
u_lfsr	100.00			100.00
u_op_err_alert	100.00			100.00
u_reg	99.41	98.74	98.86	100.00		99.47	100.00
u_reseed_ctrl	98.44	100.00	92.19	100.00		100.00	100.00
u_seed_anchor	0.00	0.00
u_sideload_ctrl	98.49	100.00	92.45		100.00	100.00	100.00
u_sw_binding_regwen	98.25	100.00	94.74			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr

	Line No.	Total	Covered	Percent
TOTAL		75	72	96.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	353	1	1	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	437	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	473	1	0	0.00
CONT_ASSIGN	474	1	0	0.00
CONT_ASSIGN	475	1	0	0.00
CONT_ASSIGN	483	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	489	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	544	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	672	1	1	100.00
CONT_ASSIGN	673	1	1	100.00
CONT_ASSIGN	674	1	1	100.00
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	677	1	1	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	680	1	1	100.00
CONT_ASSIGN	681	1	1	100.00
CONT_ASSIGN	682	1	1	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
CONT_ASSIGN	685	1	1	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	687	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
ALWAYS	723	5	5	100.00
CONT_ASSIGN	733	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	781	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
210	1	1
234	1	1
235	1	1
237	1	1
238	1	1
271	2	2
275	1	1
326	1	1
328	1	1
346	1	1
353	1	1
369	1	1
399	1	1
404	1	1
417	1	1
419	1	1
437	1	1
444	1	1
457	1	1
459	1	1
461	1	1
462	1	1
465	1	1
470	1	1
473	0	1
474	0	1
475	0	1
483	1	1
484	1	1
487	1	1
489	1	1
499	1	1
500	1	1
501	1	1
538	1	1
539	1	1
540	1	1
541	1	1
542	1	1
543	1	1
544	1	1
545	1	1
552	1	1
553	1	1
554	1	1
555	1	1
672	1	1
673	1	1
674	1	1
676	1	1
677	1	1
678	1	1
679	1	1
680	1	1
681	1	1
682	1	1
683	1	1
684	1	1
685	1	1
686	1	1
687	1	1
688	1	1
689	1	1
713	1	1
715	1	1
718	1	1
719	1	1
723	1	1
724	1	1
725	1	1
727	1	1
728	1	1
733	1	1
750	1	1
781		unreachable

---

Cond Coverage for Module : keymgr

	Total	Covered	Percent
Conditions	183	179	97.81
Logical	183	179	97.81
Non-Logical	0	0
Event	0	0

 LINE       210
 EXPRESSION (ctrl_lfsr_en | data_lfsr_en | sideload_lfsr_en)
             ------1-----   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       336
 EXPRESSION (op_start & op_done)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       353
 EXPRESSION (reg2hw.sw_binding_regwen.qe & ((~reg2hw.sw_binding_regwen.q)))
             -------------1-------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T14
1	1	Covered	T3,T14,T15

 LINE       369
 EXPRESSION (sw_binding_regwen & cfg_regwen)
             --------1--------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       399
 EXPRESSION ((cdi_sel == 1'b0) ? reg2hw.sealing_sw_binding : ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION (cdi_sel == 1'b0)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi)
                 --------1--------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION (cdi_sel == 1'b1)
                --------1--------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       444
 EXPRESSION (creator_seed_vld & devid_vld & health_state_vld & rom_digest_vld)
             --------1-------   ----2----   --------3-------   -------4------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T84,T85,T86
1	0	1	1	Covered	T49,T87,T88
1	1	0	1	Covered	T89,T90,T21
1	1	1	0	Covered	T89,T21,T91
1	1	1	1	Covered	T1,T2,T3

 LINE       484
 EXPRESSION ((dest_sel == Aes) ? aes_seed : ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed)))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       484
 SUB-EXPRESSION (dest_sel == Aes)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       484
 SUB-EXPRESSION ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       484
 SUB-EXPRESSION (dest_sel == Kmac)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       484
 SUB-EXPRESSION ((dest_sel == Otbn) ? otbn_seed : none_seed)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       484
 SUB-EXPRESSION (dest_sel == Otbn)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       489
 EXPRESSION (invalid_stage_sel ? ({GenLfsrCopies {lfsr[31:0]}}) : ({reg2hw.key_version, reg2hw.salt, dest_seed, output_key}))
             --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       538
 EXPRESSION (adv_en | id_en | gen_en)
             ---1--   --2--   ---3--

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T2,T3,T4

 LINE       539
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~creator_seed_vld)))
             ---1--   -----------2----------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T92,T93
1	0	1	Covered	T94,T95,T92
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T22,T96,T97

 LINE       539
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       540
 EXPRESSION (adv_en & (stage_sel == OwnerInt) & ((~owner_seed_vld)))
             ---1--   -----------2-----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T23
1	0	1	Covered	T98,T99,T100
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T23

 LINE       540
 SUB-EXPRESSION (stage_sel == OwnerInt)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       541
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~devid_vld)))
             ---1--   -----------2----------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T21,T92,T101
1	0	1	Covered	T98,T94,T99
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T21,T101,T102

 LINE       541
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       542
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~health_state_vld)))
             ---1--   -----------2----------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T94,T22,T100
1	0	1	Covered	T98,T94,T95
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T22,T102,T97

 LINE       542
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       543
 EXPRESSION (gen_en & ((~key_version_vld)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T18,T24

 LINE       544
 EXPRESSION (valid_op & ((~key_vld)))
             ----1---   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       545
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~rom_digest_vld)))
             ---1--   -----------2----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T21,T99,T22
1	0	1	Covered	T98,T94,T95
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T21,T22,T102

 LINE       545
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       552
 EXPRESSION (((~key_vld)) | ((~adv_dvalid[stage_sel])))
             ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T94,T99
1	0	Covered	T1,T2,T3

 LINE       554
 EXPRESSION (((~key_vld)) | ((~key_version_vld)))
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T14
1	0	Covered	T1,T2,T3

 LINE       555
 EXPRESSION (((~key_vld)) | ((~key_version_vld)))
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T14
1	0	Covered	T1,T2,T3

 LINE       625
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(0 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       625
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T25,T26
1	0	Covered	T1,T2,T3

 LINE       625
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(1 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       625
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T25,T26
1	0	Covered	T1,T2,T3

 LINE       625
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(2 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       625
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T25,T26
1	0	Covered	T1,T2,T3

 LINE       625
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(3 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       625
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T25,T26
1	0	Covered	T1,T2,T3

 LINE       625
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(4 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       625
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T25,T26
1	0	Covered	T1,T2,T3

 LINE       625
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(5 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       625
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T25,T26
1	0	Covered	T1,T2,T3

 LINE       625
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(6 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       625
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T25,T26
1	0	Covered	T1,T2,T3

 LINE       625
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(7 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       625
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T25,T26
1	0	Covered	T1,T2,T3

 LINE       632
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(0 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       632
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T25,T26
1	0	Covered	T1,T2,T3

 LINE       632
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(1 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       632
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T25,T26
1	0	Covered	T1,T2,T3

 LINE       632
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(2 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       632
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T25,T26
1	0	Covered	T1,T2,T3

 LINE       632
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(3 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       632
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T25,T26
1	0	Covered	T1,T2,T3

 LINE       632
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(4 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       632
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T25,T26
1	0	Covered	T1,T2,T3

 LINE       632
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(5 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       632
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T25,T26
1	0	Covered	T1,T2,T3

 LINE       632
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(6 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       632
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T25,T26
1	0	Covered	T1,T2,T3

 LINE       632
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(7 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       632
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T25,T26
1	0	Covered	T1,T2,T3

 LINE       715
 EXPRESSION (fault_errs ? 1'b1 : (fault_err_ack ? 1'b0 : fault_err_req_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T13,T16

 LINE       715
 SUB-EXPRESSION (fault_err_ack ? 1'b0 : fault_err_req_q)
                 ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       719
 EXPRESSION (op_errs ? 1'b1 : (op_err_ack ? 1'b0 : op_err_req_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       719
 SUB-EXPRESSION (op_err_ack ? 1'b0 : op_err_req_q)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       733
 EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T103,T104
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T103,T104

 LINE       750
 EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
             -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T103,T104
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T103,T104

---

Toggle Coverage for Module : keymgr

	Total	Covered	Percent
Totals	67	65	97.01
Total Bits	10068	10064	99.96
Total Bits 0->1	5034	5032	99.96
Total Bits 1->0	5034	5032	99.96

Ports	67	65	97.01
Port Bits	10068	10064	99.96
Port Bits 0->1	5034	5032	99.96
Port Bits 1->0	5034	5032	99.96

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T13	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T1,T3,T13	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T3,T13	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T1,T13,T15	Yes	T1,T13,T15	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][4:1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][5]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][7:6]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][8]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][17:9]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][18]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][22:19]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][23]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][28:24]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][29]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][30]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][32:31]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][36:33]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][37]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][39:38]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][40]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][49:41]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][50]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][54:51]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][55]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][60:56]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][61]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][62]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][64:63]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][68:65]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][69]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][71:70]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][72]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][81:73]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][82]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][86:83]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][87]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][92:88]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][93]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][94]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][96:95]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][100:97]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][101]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][103:102]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][104]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][113:105]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][114]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][118:115]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][119]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][124:120]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][125]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][126]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][128:127]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][132:129]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][133]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][135:134]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][136]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][145:137]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][146]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][150:147]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][151]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][156:152]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][157]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][158]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][160:159]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][164:161]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][165]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][167:166]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][168]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][177:169]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][178]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][182:179]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][183]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][188:184]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][189]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][190]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][192:191]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][196:193]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][197]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][199:198]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][200]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][209:201]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][210]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][214:211]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][215]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][220:216]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][221]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][222]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][224:223]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][228:225]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][229]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][231:230]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][232]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][241:233]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][242]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][246:243]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][247]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][252:248]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][253]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][254]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][255]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][8:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][9]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][23:10]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][24]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][30:25]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][31]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][40:32]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][41]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][55:42]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][56]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][62:57]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][63]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][72:64]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][73]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][87:74]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][88]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][94:89]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][95]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][104:96]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][105]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][119:106]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][120]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][126:121]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][127]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][136:128]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][137]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][151:138]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][152]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][158:153]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][159]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][168:160]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][169]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][183:170]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][184]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][190:185]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][191]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][200:192]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][201]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][215:202]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][216]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][222:217]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][223]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][232:224]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][233]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][247:234]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][248]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][254:249]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1][255]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.valid	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	OUTPUT
kmac_key_o.key[1:0][255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_key_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][4:1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][5]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][7:6]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][8]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][17:9]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][18]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][22:19]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][23]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][28:24]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][29]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][30]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][32:31]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][36:33]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][37]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][39:38]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][40]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][49:41]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][50]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][54:51]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][55]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][60:56]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][61]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][62]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][64:63]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][68:65]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][69]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][71:70]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][72]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][81:73]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][82]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][86:83]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][87]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][92:88]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][93]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][94]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][96:95]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][100:97]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][101]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][103:102]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][104]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][113:105]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][114]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][118:115]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][119]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][124:120]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][125]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][126]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][128:127]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][132:129]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][133]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][135:134]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][136]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][145:137]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][146]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][150:147]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][151]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][156:152]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][157]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][158]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][160:159]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][164:161]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][165]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][167:166]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][168]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][177:169]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][178]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][182:179]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][183]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][188:184]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][189]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][190]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][192:191]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][196:193]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][197]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][199:198]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][200]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][209:201]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][210]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][214:211]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][215]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][220:216]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][221]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][222]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][224:223]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][228:225]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][229]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][231:230]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][232]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][241:233]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][242]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][246:243]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][247]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][252:248]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][253]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][254]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][256:255]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][260:257]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][261]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][263:262]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][264]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][273:265]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][274]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][278:275]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][279]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][284:280]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][285]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][286]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][288:287]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][292:289]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][293]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][295:294]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][296]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][305:297]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][306]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][310:307]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][311]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][316:312]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][317]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][318]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][320:319]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][324:321]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][325]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][327:326]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][328]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][337:329]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][338]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][342:339]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][343]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][348:344]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][349]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][350]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][352:351]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][356:353]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][357]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][359:358]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][360]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][369:361]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][370]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][374:371]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][375]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][380:376]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][381]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][382]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][383]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][8:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][9]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][23:10]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][24]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][30:25]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][31]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][40:32]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][41]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][55:42]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][56]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][62:57]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][63]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][72:64]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][73]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][87:74]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][88]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][94:89]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][95]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][104:96]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][105]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][119:106]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][120]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][126:121]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][127]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][136:128]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][137]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][151:138]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][152]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][158:153]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][159]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][168:160]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][169]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][183:170]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][184]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][190:185]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][191]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][200:192]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][201]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][215:202]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][216]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][222:217]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][223]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][232:224]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][233]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][247:234]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][248]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][254:249]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][255]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][264:256]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][265]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][279:266]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][280]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][286:281]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][287]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][296:288]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][297]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][311:298]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][312]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][318:313]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][319]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][328:320]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][329]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][343:330]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][344]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][350:345]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][351]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][360:352]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][361]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][375:362]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][376]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][382:377]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1][383]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.valid	Yes	Yes	T2,T3,T18	Yes	T2,T3,T18	OUTPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_i.error	Yes	Yes	T16,T24,T26	Yes	T1,T13,T16	INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
kmac_en_masking_i	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_en_i[3:0]	Yes	Yes	T1,T3,T15	Yes	T1,T3,T4	INPUT
lc_keymgr_div_i[127:0]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
otp_key_i.owner_seed_valid	Yes	Yes	T15,T24,T49	Yes	T15,T44,T5	INPUT
otp_key_i.owner_seed[255:0]	Yes	Yes	T3,T18,T24	Yes	T3,T18,T44	INPUT
otp_key_i.creator_seed_valid	Yes	Yes	T15,T18,T44	Yes	T15,T18,T24	INPUT
otp_key_i.creator_seed[255:0]	Yes	Yes	T15,T24,T44	Yes	T15,T44,T5	INPUT
otp_key_i.creator_root_key_share1_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share1[255:0]	Yes	Yes	T15,T44,T5	Yes	T3,T15,T44	INPUT
otp_key_i.creator_root_key_share0_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share0[255:0]	Yes	Yes	T18,T24,T49	Yes	T18,T44,T5	INPUT
otp_device_id_i[255:0]	Yes	Yes	T3,T14,T15	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][7:0]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][8]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][10:9]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][11]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][12]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][13]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][18:14]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][19]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][20]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][22:21]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][23]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][24]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][29:25]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][30]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][31]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][32]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][33]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][34]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][35]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][38:36]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][39]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][46:40]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][47]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][48]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
flash_i.seeds[0][49]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][52:50]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][53]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][54]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][55]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][56]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][57]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][58]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][62:59]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][63]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][64]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][65]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][66]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][67]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][68]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][69]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][70]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][72:71]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][75:73]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][76]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][77]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][83:78]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][84]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][85]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][86]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][87]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][89:88]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][90]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][91]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][92]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][94:93]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][95]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][96]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][101:97]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][102]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][115:103]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][116]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][117]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][118]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
flash_i.seeds[0][121:119]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][122]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
flash_i.seeds[0][123]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][124]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][125]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][127:126]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][132:128]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][133]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][134]	Yes	Yes	T3,T14,T18	Yes	T3,T14,T18	INPUT
flash_i.seeds[0][135]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][136]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
flash_i.seeds[0][137]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][138]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][139]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
flash_i.seeds[0][140]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][142:141]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][143]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][144]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][145]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][146]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][147]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][149:148]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][150]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][154:151]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][155]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][156]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][157]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][158]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][159]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][160]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][161]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][166:162]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][167]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][169:168]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][170]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][171]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][172]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][174:173]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][175]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][176]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][177]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][178]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][179]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][180]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][181]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][183:182]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][184]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][185]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][186]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][189:187]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][190]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
flash_i.seeds[0][191]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][192]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][193]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][194]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][195]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][196]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][198:197]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][199]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][200]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][203:201]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][204]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][205]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][206]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][208:207]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][209]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][211:210]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][212]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][213]	Yes	Yes	T4,T14,T15	Yes	T4,T14,T15	INPUT
flash_i.seeds[0][217:214]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][218]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][221:219]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][222]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][224:223]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][226:225]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][227]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][228]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][229]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][233:230]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][234]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][235]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][236]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][237]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][239:238]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][240]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][241]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][242]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][246:243]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][247]	Yes	Yes	T3,T14,T16	Yes	T3,T14,T16	INPUT
flash_i.seeds[0][248]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][249]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
flash_i.seeds[0][250]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][252:251]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][254:253]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[0][255]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][2:0]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][3]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][6:4]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][8:7]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][9]	Yes	Yes	T3,T18,T33	Yes	T3,T18,T33	INPUT
flash_i.seeds[1][10]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][11]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][12]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][13]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][14]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][16:15]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][17]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][24:18]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][25]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
flash_i.seeds[1][26]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][27]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][28]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][29]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][30]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][31]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][32]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][33]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][34]	Yes	Yes	T3,T14,T18	Yes	T3,T14,T18	INPUT
flash_i.seeds[1][36:35]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][37]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][38]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][41:39]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][42]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][44:43]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
flash_i.seeds[1][45]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][46]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][47]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][48]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][49]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][50]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
flash_i.seeds[1][55:51]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][56]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
flash_i.seeds[1][57]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][58]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][59]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][68:60]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][69]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][71:70]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][72]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][75:73]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][77:76]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][81:78]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][82]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][83]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][84]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
flash_i.seeds[1][85]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][86]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][93:87]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][94]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][97:95]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][98]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][100:99]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][101]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][105:102]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][106]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][110:107]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][111]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][114:112]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][115]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][116]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][120:117]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][121]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][123:122]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][124]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][125]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][126]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][131:127]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][132]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][134:133]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][135]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][148:136]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][149]	Yes	Yes	T3,T14,T18	Yes	T3,T14,T18	INPUT
flash_i.seeds[1][150]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][151]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
flash_i.seeds[1][154:152]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][155]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
flash_i.seeds[1][156]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][157]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][158]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][159]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][160]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][161]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][162]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][164:163]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][165]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][166]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][167]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][168]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][169]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][170]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
flash_i.seeds[1][176:171]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][177]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][178]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][179]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][182:180]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][183]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][184]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][185]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][187:186]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
flash_i.seeds[1][189:188]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][190]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][193:191]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][194]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][195]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][196]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][202:197]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][203]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][204]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][205]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][206]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][209:207]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][210]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][211]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][212]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][219:213]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][220]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][222:221]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][223]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][225:224]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][226]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][227]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][228]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][229]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][233:230]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][234]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][239:235]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][240]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][241]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][244:242]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][245]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][246]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][247]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][248]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][249]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][250]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][252:251]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
flash_i.seeds[1][253]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][255:254]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T3,T13,T14	Yes	T1,T3,T13	INPUT
edn_i.edn_fips	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_digest_i.valid	Yes	Yes	T87,T89,T21	Yes	T87,T89,T21	INPUT
rom_digest_i.data[255:0]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
intr_op_done_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T13,T16	Yes	T1,T13,T16	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T13,T16	Yes	T1,T13,T16	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : keymgr

	Line No.	Total	Covered	Percent
Branches		49	47	95.92
TERNARY	399	3	2	66.67
TERNARY	484	4	4	100.00
TERNARY	489	2	2	100.00
TERNARY	715	3	2	66.67
TERNARY	719	3	3	100.00
TERNARY	625	2	2	100.00
TERNARY	632	2	2	100.00
TERNARY	625	2	2	100.00
TERNARY	632	2	2	100.00
TERNARY	625	2	2	100.00
TERNARY	632	2	2	100.00
TERNARY	625	2	2	100.00
TERNARY	632	2	2	100.00
TERNARY	625	2	2	100.00
TERNARY	632	2	2	100.00
TERNARY	625	2	2	100.00
TERNARY	632	2	2	100.00
TERNARY	625	2	2	100.00
TERNARY	632	2	2	100.00
TERNARY	625	2	2	100.00
TERNARY	632	2	2	100.00
IF	723	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	399	((cdi_sel == 1'b0)) ? 
-2-:	399	((cdi_sel == 1'b1)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	484	((dest_sel == Aes)) ? 
-2-:	484	((dest_sel == Kmac)) ? 
-3-:	484	((dest_sel == Otbn)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T3,T4
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	489	(invalid_stage_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	715	(fault_errs) ? 
-2-:	715	(fault_err_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T13,T16
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	719	(op_errs) ? 
-2-:	719	(op_err_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	625	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	632	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	625	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	632	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	625	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	632	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	625	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	632	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	625	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	632	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	625	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	632	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	625	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	632	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	625	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	632	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	723	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AdvDataWidth_A	883	883	0	0
AesKeyKnownO_A	27282294	27119002	0	0
AlertKnownO_A	27282294	27119002	0	0
ErrCntMatch_A	883	883	0	0
FaultCntMatch_A	883	883	0	0
FpvSecCmCtrlCntAlertCheck_A	27282294	70	0	0
FpvSecCmCtrlDataFsmCheck_A	27282294	70	0	0
FpvSecCmCtrlMainFsmCheck_A	27282294	70	0	0
FpvSecCmCtrlOpFsmCheck_A	27282294	70	0	0
FpvSecCmKmacIfCntAlertCheck_A	27282294	70	0	0
FpvSecCmKmacIfFsmCheck_A	27282294	70	0	0
FpvSecCmRegWeOnehotCheck_A	27282294	70	0	0
FpvSecCmReseedCtrlCntAlertCheck_A	27282294	70	0	0
FpvSecCmSideloadCtrlFsmCheck_A	27282294	70	0	0
GenDataWidth_A	883	883	0	0
IdDataWidth_A	883	883	0	0
IntrKnownO_A	27282294	27119002	0	0
KmacDataKnownO_A	26801138	26641459	0	0
KmacKeyKnownO_A	27282294	27119002	0	0
KmacMaskCheck_A	883	883	0	0
LfsrWidth_A	883	883	0	0
OtbnKeyKnownO_A	27282294	27119002	0	0
OutputKeyDiff_A	883	883	0	0
StageMatch_A	883	883	0	0
TlAReadyKnownO_A	27282294	27119002	0	0
TlDValidKnownO_A	27282294	27119002	0	0

AdvDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	883	883	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

AesKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27282294	27119002	0	0
T1	4903	4784	0	0
T2	4596	4539	0	0
T3	106943	106546	0	0
T4	11916	11832	0	0
T13	6122	5988	0	0
T14	9636	9548	0	0
T15	20838	20631	0	0
T16	5868	5668	0	0
T17	1328	1233	0	0
T18	76166	75577	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27282294	27119002	0	0
T1	4903	4784	0	0
T2	4596	4539	0	0
T3	106943	106546	0	0
T4	11916	11832	0	0
T13	6122	5988	0	0
T14	9636	9548	0	0
T15	20838	20631	0	0
T16	5868	5668	0	0
T17	1328	1233	0	0
T18	76166	75577	0	0

ErrCntMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	883	883	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

FaultCntMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	883	883	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

FpvSecCmCtrlCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27282294	70	0	0
T6	26014	0	0	0
T10	64779	10	0	0
T11	0	20	0	0
T12	0	10	0	0
T21	28400	0	0	0
T34	0	20	0	0
T35	0	10	0	0
T98	8368	0	0	0
T105	240981	0	0	0
T106	104300	0	0	0
T107	9720	0	0	0
T108	4791	0	0	0
T109	7479	0	0	0
T110	35739	0	0	0

FpvSecCmCtrlDataFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27282294	70	0	0
T6	26014	0	0	0
T10	64779	10	0	0
T11	0	20	0	0
T12	0	10	0	0
T21	28400	0	0	0
T34	0	20	0	0
T35	0	10	0	0
T98	8368	0	0	0
T105	240981	0	0	0
T106	104300	0	0	0
T107	9720	0	0	0
T108	4791	0	0	0
T109	7479	0	0	0
T110	35739	0	0	0

FpvSecCmCtrlMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27282294	70	0	0
T6	26014	0	0	0
T10	64779	10	0	0
T11	0	20	0	0
T12	0	10	0	0
T21	28400	0	0	0
T34	0	20	0	0
T35	0	10	0	0
T98	8368	0	0	0
T105	240981	0	0	0
T106	104300	0	0	0
T107	9720	0	0	0
T108	4791	0	0	0
T109	7479	0	0	0
T110	35739	0	0	0

FpvSecCmCtrlOpFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27282294	70	0	0
T6	26014	0	0	0
T10	64779	10	0	0
T11	0	20	0	0
T12	0	10	0	0
T21	28400	0	0	0
T34	0	20	0	0
T35	0	10	0	0
T98	8368	0	0	0
T105	240981	0	0	0
T106	104300	0	0	0
T107	9720	0	0	0
T108	4791	0	0	0
T109	7479	0	0	0
T110	35739	0	0	0

FpvSecCmKmacIfCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27282294	70	0	0
T6	26014	0	0	0
T10	64779	10	0	0
T11	0	20	0	0
T12	0	10	0	0
T21	28400	0	0	0
T34	0	20	0	0
T35	0	10	0	0
T98	8368	0	0	0
T105	240981	0	0	0
T106	104300	0	0	0
T107	9720	0	0	0
T108	4791	0	0	0
T109	7479	0	0	0
T110	35739	0	0	0

FpvSecCmKmacIfFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27282294	70	0	0
T6	26014	0	0	0
T10	64779	10	0	0
T11	0	20	0	0
T12	0	10	0	0
T21	28400	0	0	0
T34	0	20	0	0
T35	0	10	0	0
T98	8368	0	0	0
T105	240981	0	0	0
T106	104300	0	0	0
T107	9720	0	0	0
T108	4791	0	0	0
T109	7479	0	0	0
T110	35739	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27282294	70	0	0
T6	26014	0	0	0
T10	64779	10	0	0
T11	0	20	0	0
T12	0	10	0	0
T21	28400	0	0	0
T34	0	20	0	0
T35	0	10	0	0
T98	8368	0	0	0
T105	240981	0	0	0
T106	104300	0	0	0
T107	9720	0	0	0
T108	4791	0	0	0
T109	7479	0	0	0
T110	35739	0	0	0

FpvSecCmReseedCtrlCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27282294	70	0	0
T6	26014	0	0	0
T10	64779	10	0	0
T11	0	20	0	0
T12	0	10	0	0
T21	28400	0	0	0
T34	0	20	0	0
T35	0	10	0	0
T98	8368	0	0	0
T105	240981	0	0	0
T106	104300	0	0	0
T107	9720	0	0	0
T108	4791	0	0	0
T109	7479	0	0	0
T110	35739	0	0	0

FpvSecCmSideloadCtrlFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27282294	70	0	0
T6	26014	0	0	0
T10	64779	10	0	0
T11	0	20	0	0
T12	0	10	0	0
T21	28400	0	0	0
T34	0	20	0	0
T35	0	10	0	0
T98	8368	0	0	0
T105	240981	0	0	0
T106	104300	0	0	0
T107	9720	0	0	0
T108	4791	0	0	0
T109	7479	0	0	0
T110	35739	0	0	0

GenDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	883	883	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

IdDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	883	883	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

IntrKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27282294	27119002	0	0
T1	4903	4784	0	0
T2	4596	4539	0	0
T3	106943	106546	0	0
T4	11916	11832	0	0
T13	6122	5988	0	0
T14	9636	9548	0	0
T15	20838	20631	0	0
T16	5868	5668	0	0
T17	1328	1233	0	0
T18	76166	75577	0	0

KmacDataKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26801138	26641459	0	0
T1	4903	4784	0	0
T2	4596	4539	0	0
T3	106943	106546	0	0
T4	11916	11832	0	0
T13	6122	5988	0	0
T14	9636	9548	0	0
T15	20838	20631	0	0
T16	3655	3555	0	0
T17	1328	1233	0	0
T18	76166	75577	0	0

KmacKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27282294	27119002	0	0
T1	4903	4784	0	0
T2	4596	4539	0	0
T3	106943	106546	0	0
T4	11916	11832	0	0
T13	6122	5988	0	0
T14	9636	9548	0	0
T15	20838	20631	0	0
T16	5868	5668	0	0
T17	1328	1233	0	0
T18	76166	75577	0	0

KmacMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	883	883	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

LfsrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	883	883	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

OtbnKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27282294	27119002	0	0
T1	4903	4784	0	0
T2	4596	4539	0	0
T3	106943	106546	0	0
T4	11916	11832	0	0
T13	6122	5988	0	0
T14	9636	9548	0	0
T15	20838	20631	0	0
T16	5868	5668	0	0
T17	1328	1233	0	0
T18	76166	75577	0	0

OutputKeyDiff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	883	883	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

StageMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	883	883	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27282294	27119002	0	0
T1	4903	4784	0	0
T2	4596	4539	0	0
T3	106943	106546	0	0
T4	11916	11832	0	0
T13	6122	5988	0	0
T14	9636	9548	0	0
T15	20838	20631	0	0
T16	5868	5668	0	0
T17	1328	1233	0	0
T18	76166	75577	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27282294	27119002	0	0
T1	4903	4784	0	0
T2	4596	4539	0	0
T3	106943	106546	0	0
T4	11916	11832	0	0
T13	6122	5988	0	0
T14	9636	9548	0	0
T15	20838	20631	0	0
T16	5868	5668	0	0
T17	1328	1233	0	0
T18	76166	75577	0	0