Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3576049	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

621461

1

T1

272

T2

495

T3

154

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3779470	1			T1	40430		T2	9513		T3	695
values[0x0]	207561	1			T1	74		T2	199		T3	50
values[0x1]	210479	1			T1	66		T2	207		T3	56

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2443178	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1754332

1

T1

13624

T2

3613

T3

377

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12776	1			T1	93		T3	7		T4	6
valid_sources[0x01]	22794	1			T1	144		T2	241		T3	2
valid_sources[0x02]	13909	1			T1	124		T2	601		T3	2
valid_sources[0x03]	15696	1			T1	146		T4	11		T16	2
valid_sources[0x04]	12380	1			T1	104		T3	2		T4	8
valid_sources[0x05]	49487	1			T1	187		T4	9		T18	20
valid_sources[0x06]	13846	1			T1	177		T2	1		T3	2
valid_sources[0x07]	11660	1			T1	129		T3	5		T4	5
valid_sources[0x08]	12659	1			T1	150		T3	1		T4	3
valid_sources[0x09]	11863	1			T1	192		T3	3		T4	30
valid_sources[0x0a]	12469	1			T1	126		T3	2		T4	7
valid_sources[0x0b]	21842	1			T1	194		T3	2		T4	15
valid_sources[0x0c]	12063	1			T1	121		T3	3		T4	4
valid_sources[0x0d]	12049	1			T1	128		T3	2		T18	33
valid_sources[0x0e]	12852	1			T1	173		T3	3		T4	10
valid_sources[0x0f]	17241	1			T1	132		T2	1		T3	8
valid_sources[0x10]	11816	1			T1	214		T3	4		T4	2
valid_sources[0x11]	17407	1			T1	160		T3	5		T4	8
valid_sources[0x12]	12489	1			T1	321		T2	1		T3	3
valid_sources[0x13]	12391	1			T1	127		T3	6		T4	14
valid_sources[0x14]	12202	1			T1	154		T4	11		T15	2
valid_sources[0x15]	34093	1			T1	140		T3	3		T4	6
valid_sources[0x16]	20165	1			T1	158		T3	4		T4	1
valid_sources[0x17]	13179	1			T1	140		T2	1022		T3	2
valid_sources[0x18]	19042	1			T1	181		T2	1		T3	2
valid_sources[0x19]	11615	1			T1	157		T3	4		T4	19
valid_sources[0x1a]	12678	1			T1	144		T3	1		T4	1
valid_sources[0x1b]	12860	1			T1	151		T3	2		T4	11
valid_sources[0x1c]	12096	1			T1	194		T2	1		T3	3
valid_sources[0x1d]	14932	1			T1	135		T3	3		T4	3
valid_sources[0x1e]	14180	1			T1	172		T3	4		T4	4
valid_sources[0x1f]	25076	1			T1	174		T3	3		T4	12
valid_sources[0x20]	12133	1			T1	202		T3	2		T4	11
valid_sources[0x21]	12904	1			T1	160		T3	3		T4	4
valid_sources[0x22]	12071	1			T1	202		T3	3		T4	7
valid_sources[0x23]	16432	1			T1	120		T3	4		T4	3
valid_sources[0x24]	50590	1			T1	208		T2	115		T3	5
valid_sources[0x25]	35107	1			T1	131		T3	2		T4	3
valid_sources[0x26]	13707	1			T1	160		T2	12		T3	5
valid_sources[0x27]	13911	1			T1	198		T2	1		T3	6
valid_sources[0x28]	12560	1			T1	193		T3	4		T4	20
valid_sources[0x29]	12185	1			T1	182		T3	5		T15	8
valid_sources[0x2a]	13637	1			T1	202		T3	4		T4	9
valid_sources[0x2b]	13546	1			T1	125		T2	9		T3	3
valid_sources[0x2c]	44417	1			T1	227		T3	6		T4	3
valid_sources[0x2d]	13523	1			T1	112		T3	6		T4	16
valid_sources[0x2e]	12049	1			T1	134		T3	4		T4	2
valid_sources[0x2f]	25817	1			T1	145		T3	4		T4	3
valid_sources[0x30]	12440	1			T1	183		T3	2		T4	7
valid_sources[0x31]	24716	1			T1	170		T3	9		T4	9
valid_sources[0x32]	11751	1			T1	135		T3	4		T4	6
valid_sources[0x33]	12068	1			T1	161		T3	2		T4	2
valid_sources[0x34]	14770	1			T1	136		T3	2		T4	2
valid_sources[0x35]	36371	1			T1	172		T3	4		T4	7
valid_sources[0x36]	14650	1			T1	163		T3	5		T4	1
valid_sources[0x37]	12030	1			T1	143		T3	2		T4	17
valid_sources[0x38]	15126	1			T1	191		T3	2		T4	11
valid_sources[0x39]	13081	1			T1	173		T3	4		T4	16
valid_sources[0x3a]	14451	1			T1	123		T2	175		T3	2
valid_sources[0x3b]	11876	1			T1	162		T3	3		T15	10
valid_sources[0x3c]	13670	1			T1	149		T2	20		T3	4
valid_sources[0x3d]	248223	1			T1	197		T3	2		T4	16
valid_sources[0x3e]	12985	1			T1	202		T3	6		T4	6
valid_sources[0x3f]	12249	1			T1	95		T2	28		T3	3
valid_sources[0x40]	13670	1			T1	148		T3	4		T4	12
valid_sources[0x41]	11800	1			T1	161		T4	7		T15	7
valid_sources[0x42]	11710	1			T1	154		T3	6		T4	20
valid_sources[0x43]	12620	1			T1	183		T2	413		T3	3
valid_sources[0x44]	11878	1			T1	125		T3	1		T4	9
valid_sources[0x45]	18264	1			T1	163		T3	4		T4	4
valid_sources[0x46]	12554	1			T1	221		T3	4		T4	2
valid_sources[0x47]	11940	1			T1	187		T3	5		T4	1
valid_sources[0x48]	12171	1			T1	164		T3	3		T4	7
valid_sources[0x49]	12613	1			T1	202		T2	20		T3	6
valid_sources[0x4a]	11215	1			T1	168		T3	5		T15	2
valid_sources[0x4b]	18864	1			T1	90		T3	3		T4	6
valid_sources[0x4c]	12603	1			T1	155		T3	3		T15	4
valid_sources[0x4d]	14381	1			T1	152		T3	4		T4	5
valid_sources[0x4e]	15268	1			T1	128		T3	6		T4	3
valid_sources[0x4f]	11668	1			T1	129		T3	2		T4	3
valid_sources[0x50]	20793	1			T1	151		T3	3		T4	5
valid_sources[0x51]	13322	1			T1	181		T3	8		T4	10
valid_sources[0x52]	12607	1			T1	190		T3	3		T4	3
valid_sources[0x53]	20851	1			T1	138		T3	2		T4	11
valid_sources[0x54]	20581	1			T1	184		T3	2		T4	7
valid_sources[0x55]	12712	1			T1	169		T3	2		T15	2
valid_sources[0x56]	12517	1			T1	150		T3	2		T16	2
valid_sources[0x57]	14758	1			T1	163		T3	1		T4	7
valid_sources[0x58]	12278	1			T1	121		T4	4		T16	6
valid_sources[0x59]	12682	1			T1	181		T3	2		T4	4
valid_sources[0x5a]	14197	1			T1	181		T2	11		T3	2
valid_sources[0x5b]	12243	1			T1	218		T2	1		T3	1
valid_sources[0x5c]	12502	1			T1	176		T3	2		T4	3
valid_sources[0x5d]	12180	1			T1	155		T3	7		T4	18
valid_sources[0x5e]	13114	1			T1	126		T3	3		T4	8
valid_sources[0x5f]	11559	1			T1	147		T2	1		T3	2
valid_sources[0x60]	12000	1			T1	129		T4	5		T17	1
valid_sources[0x61]	14652	1			T1	141		T2	252		T3	5
valid_sources[0x62]	12379	1			T1	243		T2	1		T3	2
valid_sources[0x63]	17282	1			T1	110		T2	1		T3	4
valid_sources[0x64]	20584	1			T1	177		T3	3		T4	3
valid_sources[0x65]	13278	1			T1	195		T2	5		T3	2
valid_sources[0x66]	11847	1			T1	121		T3	2		T4	19
valid_sources[0x67]	17502	1			T1	117		T2	857		T3	5
valid_sources[0x68]	12630	1			T1	120		T2	15		T3	1
valid_sources[0x69]	12444	1			T1	68		T2	7		T3	2
valid_sources[0x6a]	19201	1			T1	182		T2	31		T3	1
valid_sources[0x6b]	12647	1			T1	87		T2	123		T3	4
valid_sources[0x6c]	12415	1			T1	222		T3	2		T15	1
valid_sources[0x6d]	16889	1			T1	129		T3	1		T4	8
valid_sources[0x6e]	13045	1			T1	101		T3	5		T4	10
valid_sources[0x6f]	14393	1			T1	136		T3	2		T4	8
valid_sources[0x70]	16237	1			T1	195		T3	6		T4	8
valid_sources[0x71]	13258	1			T1	189		T3	6		T4	11
valid_sources[0x72]	11926	1			T1	136		T2	19		T3	4
valid_sources[0x73]	14481	1			T1	175		T2	1108		T3	3
valid_sources[0x74]	12047	1			T1	104		T3	4		T4	3
valid_sources[0x75]	13156	1			T1	186		T3	3		T4	7
valid_sources[0x76]	12495	1			T1	162		T2	1		T3	3
valid_sources[0x77]	14938	1			T1	95		T3	1		T4	2
valid_sources[0x78]	14030	1			T1	101		T2	3		T3	2
valid_sources[0x79]	12391	1			T1	128		T3	4		T4	4
valid_sources[0x7a]	13605	1			T1	144		T2	19		T15	9
valid_sources[0x7b]	13414	1			T1	153		T3	3		T4	1
valid_sources[0x7c]	12717	1			T1	174		T3	2		T4	4
valid_sources[0x7d]	12633	1			T1	173		T3	1		T4	8
valid_sources[0x7e]	14124	1			T1	162		T2	5		T3	1
valid_sources[0x7f]	15334	1			T1	151		T3	4		T4	5
valid_sources[0x80]	11803	1			T1	152		T3	3		T4	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

336346

1

T1

226

T2

222

T3

76

values[0x0]

all_enables

biggest_size

149798

1

T1

25

T2

141

T3

40

values[0x1]

all_enables

biggest_size

135317

1

T1

21

T2

132

T3

38