Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
24039839 |
23869301 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
24039839 |
23869301 |
0 |
0 |
T1 |
138306 |
138254 |
0 |
0 |
T2 |
23192 |
23101 |
0 |
0 |
T3 |
3800 |
3725 |
0 |
0 |
T4 |
7188 |
7071 |
0 |
0 |
T14 |
2878 |
2828 |
0 |
0 |
T15 |
7699 |
7619 |
0 |
0 |
T16 |
8241 |
8163 |
0 |
0 |
T17 |
2590 |
2517 |
0 |
0 |
T18 |
65857 |
65767 |
0 |
0 |
T19 |
2689 |
2615 |
0 |
0 |