Line Coverage for Module :
prim_subreg_shadow
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Module :
prim_subreg_shadow
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T116,T117,T118 |
1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T116,T117,T118 |
1 | 0 | Covered | T2,T119,T61 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T116,T117,T118 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | 1 | Covered | T116,T117,T118 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T116,T117,T118 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T116,T117,T118 |
Branch Coverage for Module :
prim_subreg_shadow
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T2,T119,T61 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_subreg_shadow
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7588 |
7588 |
0 |
0 |
T1 |
7 |
7 |
0 |
0 |
T2 |
7 |
7 |
0 |
0 |
T3 |
7 |
7 |
0 |
0 |
T4 |
7 |
7 |
0 |
0 |
T14 |
7 |
7 |
0 |
0 |
T15 |
7 |
7 |
0 |
0 |
T16 |
7 |
7 |
0 |
0 |
T17 |
7 |
7 |
0 |
0 |
T18 |
7 |
7 |
0 |
0 |
T19 |
7 |
7 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
181541101 |
179806886 |
0 |
0 |
T1 |
968142 |
967778 |
0 |
0 |
T2 |
162344 |
161707 |
0 |
0 |
T3 |
26600 |
26075 |
0 |
0 |
T4 |
50316 |
49497 |
0 |
0 |
T14 |
20146 |
19796 |
0 |
0 |
T15 |
53893 |
53333 |
0 |
0 |
T16 |
57687 |
57141 |
0 |
0 |
T17 |
18130 |
17619 |
0 |
0 |
T18 |
460999 |
460369 |
0 |
0 |
T19 |
18823 |
18305 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_control_shadowed_operation
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_control_shadowed_operation
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T116,T117,T120 |
1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T116,T117,T118 |
1 | 0 | Covered | T2,T119,T61 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T116,T117,T120 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | 1 | Covered | T117,T118,T121 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T117,T118,T121 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T116,T117,T118 |
Branch Coverage for Instance : tb.dut.u_reg.u_control_shadowed_operation
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T2,T119,T61 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_control_shadowed_operation
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1084 |
1084 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25934443 |
25686698 |
0 |
0 |
T1 |
138306 |
138254 |
0 |
0 |
T2 |
23192 |
23101 |
0 |
0 |
T3 |
3800 |
3725 |
0 |
0 |
T4 |
7188 |
7071 |
0 |
0 |
T14 |
2878 |
2828 |
0 |
0 |
T15 |
7699 |
7619 |
0 |
0 |
T16 |
8241 |
8163 |
0 |
0 |
T17 |
2590 |
2517 |
0 |
0 |
T18 |
65857 |
65767 |
0 |
0 |
T19 |
2689 |
2615 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_control_shadowed_cdi_sel
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_control_shadowed_cdi_sel
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T118,T120,T121 |
1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T117,T118,T120 |
1 | 0 | Covered | T2,T119,T61 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T118,T120,T121 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | 1 | Covered | T118,T121,T122 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T118,T121,T122 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T117,T118,T120 |
Branch Coverage for Instance : tb.dut.u_reg.u_control_shadowed_cdi_sel
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T2,T119,T61 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_control_shadowed_cdi_sel
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1084 |
1084 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25934443 |
25686698 |
0 |
0 |
T1 |
138306 |
138254 |
0 |
0 |
T2 |
23192 |
23101 |
0 |
0 |
T3 |
3800 |
3725 |
0 |
0 |
T4 |
7188 |
7071 |
0 |
0 |
T14 |
2878 |
2828 |
0 |
0 |
T15 |
7699 |
7619 |
0 |
0 |
T16 |
8241 |
8163 |
0 |
0 |
T17 |
2590 |
2517 |
0 |
0 |
T18 |
65857 |
65767 |
0 |
0 |
T19 |
2689 |
2615 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_control_shadowed_dest_sel
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_control_shadowed_dest_sel
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T117,T120,T123 |
1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T116,T117,T118 |
1 | 0 | Covered | T2,T119,T61 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T117,T120,T123 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | 1 | Covered | T116,T118,T120 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T116,T118,T120 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T116,T117,T118 |
Branch Coverage for Instance : tb.dut.u_reg.u_control_shadowed_dest_sel
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T2,T119,T61 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_control_shadowed_dest_sel
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1084 |
1084 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25934443 |
25686698 |
0 |
0 |
T1 |
138306 |
138254 |
0 |
0 |
T2 |
23192 |
23101 |
0 |
0 |
T3 |
3800 |
3725 |
0 |
0 |
T4 |
7188 |
7071 |
0 |
0 |
T14 |
2878 |
2828 |
0 |
0 |
T15 |
7699 |
7619 |
0 |
0 |
T16 |
8241 |
8163 |
0 |
0 |
T17 |
2590 |
2517 |
0 |
0 |
T18 |
65857 |
65767 |
0 |
0 |
T19 |
2689 |
2615 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_reseed_interval_shadowed
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_reseed_interval_shadowed
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T117,T123,T124 |
1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T116,T117,T123 |
1 | 0 | Covered | T61,T5,T71 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T117,T123,T124 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | 1 | Covered | T117,T118,T124 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T117,T118,T124 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T116,T117,T123 |
Branch Coverage for Instance : tb.dut.u_reg.u_reseed_interval_shadowed
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T61,T5,T71 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_reseed_interval_shadowed
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1084 |
1084 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25934443 |
25686698 |
0 |
0 |
T1 |
138306 |
138254 |
0 |
0 |
T2 |
23192 |
23101 |
0 |
0 |
T3 |
3800 |
3725 |
0 |
0 |
T4 |
7188 |
7071 |
0 |
0 |
T14 |
2878 |
2828 |
0 |
0 |
T15 |
7699 |
7619 |
0 |
0 |
T16 |
8241 |
8163 |
0 |
0 |
T17 |
2590 |
2517 |
0 |
0 |
T18 |
65857 |
65767 |
0 |
0 |
T19 |
2689 |
2615 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_max_creator_key_ver_shadowed
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_max_creator_key_ver_shadowed
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T117,T124,T121 |
1 | 1 | Covered | T2,T3,T14 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T116,T117,T118 |
1 | 0 | Covered | T61,T5,T71 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T14 |
1 | 1 | 0 | Covered | T117,T124,T121 |
1 | 1 | 1 | Covered | T2,T3,T14 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T2,T3,T14 |
1 | 0 | 1 | 1 | Covered | T2,T3,T14 |
1 | 1 | 0 | 1 | Covered | T120,T123,T124 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T2,T3,T14 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T2,T3,T14 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T14 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T14 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T14 |
1 | 0 | Covered | T2,T3,T14 |
1 | 1 | Covered | T120,T123,T124 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T116,T117,T118 |
Branch Coverage for Instance : tb.dut.u_reg.u_max_creator_key_ver_shadowed
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T14 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T3,T14 |
0 |
0 |
1 |
Covered |
T61,T5,T71 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_max_creator_key_ver_shadowed
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1084 |
1084 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25934443 |
25686698 |
0 |
0 |
T1 |
138306 |
138254 |
0 |
0 |
T2 |
23192 |
23101 |
0 |
0 |
T3 |
3800 |
3725 |
0 |
0 |
T4 |
7188 |
7071 |
0 |
0 |
T14 |
2878 |
2828 |
0 |
0 |
T15 |
7699 |
7619 |
0 |
0 |
T16 |
8241 |
8163 |
0 |
0 |
T17 |
2590 |
2517 |
0 |
0 |
T18 |
65857 |
65767 |
0 |
0 |
T19 |
2689 |
2615 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_max_owner_int_key_ver_shadowed
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_max_owner_int_key_ver_shadowed
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T116,T117,T123 |
1 | 1 | Covered | T3,T14,T16 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T116,T117,T120 |
1 | 0 | Covered | T61,T5,T71 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T3,T14,T16 |
1 | 1 | 0 | Covered | T116,T117,T123 |
1 | 1 | 1 | Covered | T3,T14,T16 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T3,T14,T16 |
1 | 0 | 1 | 1 | Covered | T3,T14,T16 |
1 | 1 | 0 | 1 | Covered | T117,T121,T125 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T3,T14,T16 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T3,T14,T16 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T3,T14,T16 |
1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T14,T16 |
1 | 0 | Covered | T3,T14,T16 |
1 | 1 | Covered | T117,T121,T125 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T116,T117,T120 |
Branch Coverage for Instance : tb.dut.u_reg.u_max_owner_int_key_ver_shadowed
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T14,T16 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T3,T14,T16 |
0 |
0 |
1 |
Covered |
T61,T5,T71 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_max_owner_int_key_ver_shadowed
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1084 |
1084 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25934443 |
25686698 |
0 |
0 |
T1 |
138306 |
138254 |
0 |
0 |
T2 |
23192 |
23101 |
0 |
0 |
T3 |
3800 |
3725 |
0 |
0 |
T4 |
7188 |
7071 |
0 |
0 |
T14 |
2878 |
2828 |
0 |
0 |
T15 |
7699 |
7619 |
0 |
0 |
T16 |
8241 |
8163 |
0 |
0 |
T17 |
2590 |
2517 |
0 |
0 |
T18 |
65857 |
65767 |
0 |
0 |
T19 |
2689 |
2615 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T121,T125,T126 |
1 | 1 | Covered | T2,T3,T14 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T117,T120,T121 |
1 | 0 | Covered | T61,T5,T71 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T14 |
1 | 1 | 0 | Covered | T121,T125,T126 |
1 | 1 | 1 | Covered | T2,T3,T14 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T2,T3,T14 |
1 | 0 | 1 | 1 | Covered | T2,T3,T14 |
1 | 1 | 0 | 1 | Covered | T117,T121,T125 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T2,T3,T14 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T2,T3,T14 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T14 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T14 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T14 |
1 | 0 | Covered | T2,T3,T14 |
1 | 1 | Covered | T117,T121,T125 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T117,T120,T121 |
Branch Coverage for Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T14 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T3,T14 |
0 |
0 |
1 |
Covered |
T61,T5,T71 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1084 |
1084 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25934443 |
25686698 |
0 |
0 |
T1 |
138306 |
138254 |
0 |
0 |
T2 |
23192 |
23101 |
0 |
0 |
T3 |
3800 |
3725 |
0 |
0 |
T4 |
7188 |
7071 |
0 |
0 |
T14 |
2878 |
2828 |
0 |
0 |
T15 |
7699 |
7619 |
0 |
0 |
T16 |
8241 |
8163 |
0 |
0 |
T17 |
2590 |
2517 |
0 |
0 |
T18 |
65857 |
65767 |
0 |
0 |
T19 |
2689 |
2615 |
0 |
0 |