Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25934443	15503	0	0
attest_sw_binding_0_rd_A	25934443	4498	0	0
attest_sw_binding_1_rd_A	25934443	4537	0	0
attest_sw_binding_2_rd_A	25934443	4612	0	0
attest_sw_binding_3_rd_A	25934443	4672	0	0
attest_sw_binding_4_rd_A	25934443	4523	0	0
attest_sw_binding_5_rd_A	25934443	4399	0	0
attest_sw_binding_6_rd_A	25934443	4417	0	0
attest_sw_binding_7_rd_A	25934443	4603	0	0
intr_enable_rd_A	25934443	5500	0	0
key_version_rd_A	25934443	4553	0	0
max_creator_key_ver_regwen_rd_A	25934443	4477	0	0
max_owner_int_key_ver_regwen_rd_A	25934443	4492	0	0
max_owner_key_ver_regwen_rd_A	25934443	4587	0	0
reseed_interval_regwen_rd_A	25934443	4649	0	0
salt_0_rd_A	25934443	4372	0	0
salt_1_rd_A	25934443	4478	0	0
salt_2_rd_A	25934443	4533	0	0
salt_3_rd_A	25934443	4452	0	0
salt_4_rd_A	25934443	4683	0	0
salt_5_rd_A	25934443	4594	0	0
salt_6_rd_A	25934443	4487	0	0
salt_7_rd_A	25934443	4564	0	0
sealing_sw_binding_0_rd_A	25934443	4421	0	0
sealing_sw_binding_1_rd_A	25934443	4491	0	0
sealing_sw_binding_2_rd_A	25934443	4721	0	0
sealing_sw_binding_3_rd_A	25934443	4482	0	0
sealing_sw_binding_4_rd_A	25934443	4540	0	0
sealing_sw_binding_5_rd_A	25934443	4634	0	0
sealing_sw_binding_6_rd_A	25934443	4691	0	0
sealing_sw_binding_7_rd_A	25934443	4281	0	0
sideload_clear_rd_A	25934443	4593	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	15503	0	0
T5	0	1319	0	0
T61	35066	1504	0	0
T64	43221	0	0	0
T65	0	76	0	0
T66	2184	0	0	0
T71	0	25	0	0
T93	1839	0	0	0
T106	1621	0	0	0
T128	0	271	0	0
T130	0	251	0	0
T131	0	416	0	0
T132	0	931	0	0
T133	4239	0	0	0
T134	3456	0	0	0
T135	4995	0	0	0
T136	10422	0	0	0
T137	7438	0	0	0
T140	0	138	0	0
T141	0	210	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4498	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	22	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	94	0	0
T117	0	243	0	0
T128	0	90	0	0
T156	0	257	0	0
T183	0	60	0	0
T184	0	1	0	0
T185	0	59	0	0
T186	0	37	0	0
T187	0	40	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4537	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	31	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	99	0	0
T117	0	212	0	0
T128	0	56	0	0
T156	0	229	0	0
T183	0	64	0	0
T184	0	24	0	0
T185	0	42	0	0
T186	0	58	0	0
T187	0	36	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4612	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	17	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	134	0	0
T117	0	183	0	0
T128	0	77	0	0
T156	0	245	0	0
T183	0	47	0	0
T184	0	23	0	0
T185	0	37	0	0
T186	0	32	0	0
T187	0	68	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4672	0	0
T6	12706	0	0	0
T62	30819	3	0	0
T71	27392	30	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	111	0	0
T128	0	66	0	0
T156	0	235	0	0
T183	0	54	0	0
T184	0	31	0	0
T185	0	28	0	0
T186	0	48	0	0
T187	0	47	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4523	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	20	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	111	0	0
T117	0	202	0	0
T128	0	74	0	0
T156	0	227	0	0
T183	0	47	0	0
T184	0	16	0	0
T185	0	17	0	0
T186	0	32	0	0
T187	0	53	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4399	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	36	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	94	0	0
T117	0	217	0	0
T128	0	60	0	0
T156	0	198	0	0
T183	0	28	0	0
T184	0	49	0	0
T185	0	45	0	0
T186	0	35	0	0
T187	0	50	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4417	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	27	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	124	0	0
T117	0	207	0	0
T128	0	70	0	0
T156	0	204	0	0
T183	0	31	0	0
T184	0	19	0	0
T185	0	19	0	0
T186	0	48	0	0
T187	0	73	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4603	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	21	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	111	0	0
T117	0	214	0	0
T128	0	58	0	0
T156	0	210	0	0
T183	0	61	0	0
T184	0	19	0	0
T185	0	23	0	0
T186	0	41	0	0
T187	0	48	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	5500	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	21	0	0
T74	0	79	0	0
T75	0	19	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T128	0	84	0	0
T188	0	12	0	0
T189	0	33	0	0
T190	0	53	0	0
T191	0	8	0	0
T192	0	15	0	0
T193	0	36	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4553	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	25	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	96	0	0
T117	0	236	0	0
T128	0	99	0	0
T156	0	194	0	0
T183	0	54	0	0
T184	0	15	0	0
T185	0	29	0	0
T186	0	66	0	0
T187	0	44	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4477	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	34	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	100	0	0
T128	0	71	0	0
T156	0	236	0	0
T183	0	48	0	0
T184	0	42	0	0
T185	0	33	0	0
T186	0	75	0	0
T187	0	22	0	0
T194	0	2	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4492	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	20	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	121	0	0
T117	0	213	0	0
T128	0	44	0	0
T156	0	240	0	0
T183	0	46	0	0
T184	0	24	0	0
T185	0	30	0	0
T186	0	47	0	0
T187	0	34	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4587	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	33	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	116	0	0
T117	0	191	0	0
T128	0	58	0	0
T156	0	178	0	0
T183	0	22	0	0
T184	0	31	0	0
T185	0	27	0	0
T186	0	46	0	0
T187	0	58	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4649	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	26	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	114	0	0
T117	0	224	0	0
T128	0	76	0	0
T156	0	258	0	0
T183	0	51	0	0
T184	0	21	0	0
T185	0	53	0	0
T186	0	46	0	0
T187	0	46	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4372	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	24	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	84	0	0
T117	0	235	0	0
T128	0	55	0	0
T156	0	221	0	0
T183	0	40	0	0
T184	0	4	0	0
T185	0	20	0	0
T186	0	45	0	0
T187	0	33	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4478	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	27	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	96	0	0
T117	0	200	0	0
T128	0	48	0	0
T156	0	220	0	0
T183	0	53	0	0
T184	0	10	0	0
T185	0	31	0	0
T186	0	59	0	0
T187	0	41	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4533	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	25	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	108	0	0
T117	0	254	0	0
T128	0	52	0	0
T156	0	207	0	0
T183	0	47	0	0
T184	0	20	0	0
T185	0	15	0	0
T186	0	79	0	0
T187	0	52	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4452	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	28	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	93	0	0
T117	0	247	0	0
T128	0	59	0	0
T156	0	260	0	0
T183	0	61	0	0
T184	0	9	0	0
T185	0	20	0	0
T186	0	72	0	0
T187	0	65	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4683	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	21	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	111	0	0
T117	0	228	0	0
T128	0	69	0	0
T156	0	210	0	0
T183	0	54	0	0
T184	0	16	0	0
T185	0	32	0	0
T186	0	35	0	0
T187	0	46	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4594	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	22	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	92	0	0
T117	0	205	0	0
T128	0	85	0	0
T156	0	242	0	0
T183	0	46	0	0
T184	0	25	0	0
T185	0	42	0	0
T186	0	45	0	0
T187	0	63	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4487	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	25	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	114	0	0
T117	0	208	0	0
T128	0	59	0	0
T156	0	234	0	0
T183	0	53	0	0
T184	0	20	0	0
T185	0	29	0	0
T186	0	64	0	0
T187	0	51	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4564	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	18	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	119	0	0
T117	0	207	0	0
T128	0	79	0	0
T156	0	234	0	0
T183	0	32	0	0
T184	0	32	0	0
T185	0	46	0	0
T186	0	55	0	0
T187	0	58	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4421	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	30	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	99	0	0
T117	0	196	0	0
T128	0	61	0	0
T156	0	222	0	0
T183	0	62	0	0
T184	0	25	0	0
T185	0	32	0	0
T186	0	69	0	0
T187	0	71	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4491	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	27	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	102	0	0
T117	0	224	0	0
T128	0	90	0	0
T156	0	249	0	0
T183	0	53	0	0
T184	0	7	0	0
T185	0	15	0	0
T186	0	45	0	0
T187	0	58	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4721	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	28	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	97	0	0
T117	0	240	0	0
T128	0	88	0	0
T156	0	231	0	0
T183	0	63	0	0
T184	0	34	0	0
T185	0	24	0	0
T186	0	68	0	0
T187	0	43	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4482	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	24	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	106	0	0
T117	0	205	0	0
T128	0	58	0	0
T156	0	186	0	0
T183	0	56	0	0
T184	0	22	0	0
T185	0	18	0	0
T186	0	71	0	0
T187	0	41	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4540	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	27	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	110	0	0
T117	0	223	0	0
T128	0	46	0	0
T156	0	231	0	0
T183	0	66	0	0
T184	0	8	0	0
T185	0	47	0	0
T186	0	55	0	0
T187	0	64	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4634	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	22	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	97	0	0
T117	0	224	0	0
T128	0	55	0	0
T156	0	197	0	0
T183	0	45	0	0
T184	0	12	0	0
T185	0	53	0	0
T186	0	38	0	0
T187	0	35	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4691	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	31	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	121	0	0
T117	0	205	0	0
T128	0	56	0	0
T156	0	246	0	0
T183	0	63	0	0
T184	0	14	0	0
T185	0	42	0	0
T186	0	53	0	0
T187	0	45	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4281	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	22	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	111	0	0
T117	0	231	0	0
T128	0	55	0	0
T156	0	214	0	0
T183	0	55	0	0
T184	0	17	0	0
T185	0	14	0	0
T186	0	54	0	0
T187	0	49	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25934443	4593	0	0
T6	12706	0	0	0
T62	30819	0	0	0
T71	27392	35	0	0
T80	21426	0	0	0
T81	5236	0	0	0
T82	3751	0	0	0
T83	8955	0	0	0
T84	8157	0	0	0
T85	8128	0	0	0
T86	11341	0	0	0
T116	0	92	0	0
T117	0	198	0	0
T128	0	71	0	0
T156	0	220	0	0
T183	0	53	0	0
T184	0	8	0	0
T185	0	32	0	0
T186	0	56	0	0
T187	0	39	0	0