Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2988323	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

575893

1

T1

359

T2

165

T3

471

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3166845	1			T1	769		T2	225		T3	2537
values[0x0]	196991	1			T1	158		T2	59		T3	187
values[0x1]	200380	1			T1	113		T2	58		T3	177

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2046749	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1517467

1

T1

572

T2

215

T3

1218

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10175	1			T1	5		T3	1		T12	12
valid_sources[0x01]	25731	1			T1	2		T3	2		T13	7
valid_sources[0x02]	14341	1			T1	4		T3	14		T12	3
valid_sources[0x03]	11003	1			T1	3		T3	4		T12	5
valid_sources[0x04]	11536	1			T1	4		T3	11		T12	1
valid_sources[0x05]	11561	1			T1	4		T3	26		T12	2
valid_sources[0x06]	10375	1			T1	4		T3	7		T12	2
valid_sources[0x07]	10948	1			T1	3		T3	32		T12	1
valid_sources[0x08]	10239	1			T1	3		T3	29		T12	5
valid_sources[0x09]	11195	1			T1	3		T3	4		T12	6
valid_sources[0x0a]	9867	1			T1	5		T3	19		T14	3
valid_sources[0x0b]	10851	1			T1	3		T3	19		T12	3
valid_sources[0x0c]	10370	1			T3	9		T12	4		T13	16
valid_sources[0x0d]	9439	1			T1	4		T3	4		T12	6
valid_sources[0x0e]	13235	1			T1	5		T3	23		T12	3
valid_sources[0x0f]	41771	1			T1	4		T3	16		T12	3
valid_sources[0x10]	11640	1			T1	6		T3	12		T12	3
valid_sources[0x11]	10459	1			T1	5		T12	10		T14	1
valid_sources[0x12]	17488	1			T1	10		T3	12		T16	12
valid_sources[0x13]	9141	1			T1	3		T3	13		T12	3
valid_sources[0x14]	9417	1			T1	3		T3	6		T12	6
valid_sources[0x15]	13896	1			T1	2		T3	4		T12	6
valid_sources[0x16]	10136	1			T1	1		T3	6		T12	1
valid_sources[0x17]	11461	1			T1	7		T3	9		T14	4
valid_sources[0x18]	20101	1			T1	6		T12	8		T14	4
valid_sources[0x19]	9440	1			T1	4		T3	2		T12	5
valid_sources[0x1a]	14232	1			T1	6		T3	1		T12	9
valid_sources[0x1b]	9285	1			T1	4		T3	11		T12	1
valid_sources[0x1c]	10552	1			T1	2		T3	2		T12	4
valid_sources[0x1d]	10831	1			T1	6		T3	7		T12	3
valid_sources[0x1e]	10009	1			T1	9		T3	40		T12	6
valid_sources[0x1f]	10103	1			T1	3		T12	6		T14	4
valid_sources[0x20]	9526	1			T1	8		T3	10		T12	6
valid_sources[0x21]	9903	1			T1	2		T3	31		T12	3
valid_sources[0x22]	12592	1			T1	2		T3	10		T12	3
valid_sources[0x23]	10740	1			T1	9		T3	10		T12	3
valid_sources[0x24]	10705	1			T1	1		T3	28		T12	3
valid_sources[0x25]	13993	1			T1	5		T12	2		T14	6
valid_sources[0x26]	12336	1			T1	3		T3	7		T12	4
valid_sources[0x27]	9840	1			T1	4		T3	4		T12	7
valid_sources[0x28]	10961	1			T1	3		T3	14		T12	4
valid_sources[0x29]	13597	1			T1	3		T3	11		T12	4
valid_sources[0x2a]	57372	1			T1	4		T3	9		T13	11
valid_sources[0x2b]	10389	1			T1	2		T3	17		T12	3
valid_sources[0x2c]	14283	1			T1	2		T3	8		T12	8
valid_sources[0x2d]	81181	1			T1	2		T3	8		T12	1
valid_sources[0x2e]	11825	1			T1	7		T3	6		T12	6
valid_sources[0x2f]	11430	1			T1	5		T3	24		T12	6
valid_sources[0x30]	14906	1			T1	5		T3	42		T12	2
valid_sources[0x31]	13382	1			T1	7		T3	9		T12	1
valid_sources[0x32]	9972	1			T1	7		T3	2		T12	2
valid_sources[0x33]	11024	1			T1	7		T3	17		T12	5
valid_sources[0x34]	15172	1			T1	1		T3	3		T12	2
valid_sources[0x35]	12249	1			T1	6		T3	2		T14	7
valid_sources[0x36]	20268	1			T1	3		T3	1		T12	2
valid_sources[0x37]	14324	1			T1	4		T3	9		T12	3
valid_sources[0x38]	10020	1			T1	5		T3	11		T14	8
valid_sources[0x39]	11794	1			T1	5		T3	9		T12	3
valid_sources[0x3a]	13102	1			T1	5		T3	5		T13	16
valid_sources[0x3b]	10408	1			T1	4		T3	19		T12	6
valid_sources[0x3c]	9906	1			T1	3		T3	7		T12	3
valid_sources[0x3d]	12335	1			T1	4		T3	1		T12	3
valid_sources[0x3e]	14669	1			T1	5		T3	18		T12	5
valid_sources[0x3f]	14749	1			T1	2		T3	15		T12	5
valid_sources[0x40]	9527	1			T1	2		T3	10		T12	1
valid_sources[0x41]	11683	1			T1	8		T3	8		T13	6
valid_sources[0x42]	9808	1			T1	2		T12	3		T14	1
valid_sources[0x43]	19659	1			T1	4		T3	12		T12	11
valid_sources[0x44]	10631	1			T1	2		T12	3		T13	1
valid_sources[0x45]	10092	1			T1	3		T3	2		T12	3
valid_sources[0x46]	11079	1			T1	10		T3	1		T12	7
valid_sources[0x47]	9193	1			T1	5		T3	3		T12	2
valid_sources[0x48]	11065	1			T1	4		T3	36		T12	1
valid_sources[0x49]	9521	1			T1	1		T12	7		T13	14
valid_sources[0x4a]	11302	1			T1	3		T3	9		T12	1
valid_sources[0x4b]	10729	1			T1	4		T3	43		T14	3
valid_sources[0x4c]	14528	1			T1	4		T3	5		T12	6
valid_sources[0x4d]	10836	1			T1	6		T3	11		T12	1
valid_sources[0x4e]	10412	1			T1	2		T3	4		T12	7
valid_sources[0x4f]	10852	1			T1	3		T3	15		T12	6
valid_sources[0x50]	11285	1			T1	6		T3	1		T12	2
valid_sources[0x51]	12385	1			T1	3		T12	2		T13	9
valid_sources[0x52]	12690	1			T1	6		T3	12		T12	4
valid_sources[0x53]	12447	1			T1	4		T3	5		T12	1
valid_sources[0x54]	12436	1			T1	8		T12	5		T13	9
valid_sources[0x55]	13869	1			T1	8		T3	4		T12	1
valid_sources[0x56]	19320	1			T3	9		T12	1		T13	16
valid_sources[0x57]	13419	1			T3	9		T12	2		T18	4
valid_sources[0x58]	29377	1			T1	4		T3	4		T12	4
valid_sources[0x59]	9900	1			T1	8		T3	30		T12	10
valid_sources[0x5a]	11459	1			T1	2		T3	12		T12	3
valid_sources[0x5b]	9489	1			T1	5		T3	2		T12	5
valid_sources[0x5c]	12776	1			T1	5		T3	7		T12	5
valid_sources[0x5d]	12352	1			T1	4		T3	8		T12	6
valid_sources[0x5e]	12144	1			T1	7		T3	24		T12	2
valid_sources[0x5f]	9944	1			T1	2		T3	20		T12	5
valid_sources[0x60]	11344	1			T1	1		T3	5		T12	2
valid_sources[0x61]	11117	1			T1	3		T3	28		T12	5
valid_sources[0x62]	144221	1			T1	6		T3	4		T12	3
valid_sources[0x63]	10434	1			T1	7		T3	13		T12	8
valid_sources[0x64]	10059	1			T1	1		T3	6		T12	3
valid_sources[0x65]	10251	1			T1	4		T3	11		T12	3
valid_sources[0x66]	9811	1			T1	1		T3	46		T13	18
valid_sources[0x67]	10009	1			T1	5		T3	8		T12	6
valid_sources[0x68]	9543	1			T1	1		T3	8		T12	10
valid_sources[0x69]	9593	1			T1	3		T3	50		T12	2
valid_sources[0x6a]	11609	1			T1	4		T3	12		T12	3
valid_sources[0x6b]	17001	1			T1	3		T3	4		T12	1
valid_sources[0x6c]	11004	1			T1	2		T3	9		T12	3
valid_sources[0x6d]	15904	1			T1	4		T3	16		T12	9
valid_sources[0x6e]	10373	1			T1	6		T3	5		T12	4
valid_sources[0x6f]	13433	1			T1	2		T3	5		T12	5
valid_sources[0x70]	9695	1			T1	3		T3	34		T14	1
valid_sources[0x71]	14564	1			T1	4		T3	2		T12	6
valid_sources[0x72]	16790	1			T1	4		T3	4		T12	3
valid_sources[0x73]	9472	1			T1	5		T3	2		T12	2
valid_sources[0x74]	9526	1			T1	4		T3	21		T12	3
valid_sources[0x75]	16000	1			T1	1		T3	21		T12	1
valid_sources[0x76]	11283	1			T1	8		T3	1		T12	5
valid_sources[0x77]	10170	1			T1	6		T3	14		T12	2
valid_sources[0x78]	13886	1			T1	5		T3	27		T12	6
valid_sources[0x79]	13234	1			T1	5		T12	3		T13	4
valid_sources[0x7a]	9939	1			T1	1		T3	29		T12	4
valid_sources[0x7b]	10269	1			T3	34		T12	7		T13	1
valid_sources[0x7c]	11350	1			T1	5		T3	16		T12	1
valid_sources[0x7d]	10288	1			T1	5		T3	1		T12	8
valid_sources[0x7e]	10120	1			T1	6		T3	3		T12	4
valid_sources[0x7f]	9834	1			T1	5		T12	1		T13	7
valid_sources[0x80]	12184	1			T1	4		T3	4		T12	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

304083

1

T1

181

T2

77

T3

214

values[0x0]

all_enables

biggest_size

142775

1

T1

110

T2

46

T3

129

values[0x1]

all_enables

biggest_size

129035

1

T1

68

T2

42

T3

128