Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
19454279 |
19307173 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19454279 |
19307173 |
0 |
0 |
T1 |
5045 |
4945 |
0 |
0 |
T2 |
4003 |
3917 |
0 |
0 |
T3 |
24868 |
24792 |
0 |
0 |
T12 |
8296 |
8225 |
0 |
0 |
T13 |
9166 |
9096 |
0 |
0 |
T14 |
11507 |
11426 |
0 |
0 |
T15 |
7787 |
7714 |
0 |
0 |
T16 |
2689 |
2596 |
0 |
0 |
T17 |
6858 |
6790 |
0 |
0 |
T18 |
15069 |
15019 |
0 |
0 |