Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	21227055	18243	0	0
attest_sw_binding_0_rd_A	21227055	2790	0	0
attest_sw_binding_1_rd_A	21227055	2863	0	0
attest_sw_binding_2_rd_A	21227055	2711	0	0
attest_sw_binding_3_rd_A	21227055	2848	0	0
attest_sw_binding_4_rd_A	21227055	2825	0	0
attest_sw_binding_5_rd_A	21227055	2960	0	0
attest_sw_binding_6_rd_A	21227055	2960	0	0
attest_sw_binding_7_rd_A	21227055	2913	0	0
intr_enable_rd_A	21227055	3382	0	0
key_version_rd_A	21227055	3050	0	0
max_creator_key_ver_regwen_rd_A	21227055	3074	0	0
max_owner_int_key_ver_regwen_rd_A	21227055	2784	0	0
max_owner_key_ver_regwen_rd_A	21227055	2840	0	0
reseed_interval_regwen_rd_A	21227055	2740	0	0
salt_0_rd_A	21227055	2790	0	0
salt_1_rd_A	21227055	2893	0	0
salt_2_rd_A	21227055	2937	0	0
salt_3_rd_A	21227055	2635	0	0
salt_4_rd_A	21227055	2784	0	0
salt_5_rd_A	21227055	2907	0	0
salt_6_rd_A	21227055	2863	0	0
salt_7_rd_A	21227055	2895	0	0
sealing_sw_binding_0_rd_A	21227055	2708	0	0
sealing_sw_binding_1_rd_A	21227055	3032	0	0
sealing_sw_binding_2_rd_A	21227055	2906	0	0
sealing_sw_binding_3_rd_A	21227055	3015	0	0
sealing_sw_binding_4_rd_A	21227055	2875	0	0
sealing_sw_binding_5_rd_A	21227055	2896	0	0
sealing_sw_binding_6_rd_A	21227055	3034	0	0
sealing_sw_binding_7_rd_A	21227055	2830	0	0
sideload_clear_rd_A	21227055	2788	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	18243	0	0
T48	11672	314	0	0
T52	0	210	0	0
T57	54770	218	0	0
T70	0	213	0	0
T72	0	54	0	0
T115	0	1817	0	0
T118	0	125	0	0
T131	0	436	0	0
T132	0	1473	0	0
T134	3689	0	0	0
T135	2086	0	0	0
T136	4353	0	0	0
T137	12065	0	0	0
T138	5933	0	0	0
T139	21185	0	0	0
T140	19251	0	0	0
T141	994	0	0	0
T142	0	615	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2790	0	0
T52	41083	69	0	0
T56	14361	0	0	0
T72	28642	17	0	0
T150	0	19	0	0
T152	0	21	0	0
T160	0	30	0	0
T182	0	30	0	0
T183	0	29	0	0
T184	0	6	0	0
T185	0	17	0	0
T186	0	29	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2863	0	0
T52	41083	98	0	0
T56	14361	0	0	0
T72	28642	32	0	0
T150	0	45	0	0
T152	0	36	0	0
T160	0	11	0	0
T182	0	25	0	0
T183	0	37	0	0
T184	0	16	0	0
T185	0	33	0	0
T186	0	8	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2711	0	0
T52	41083	33	0	0
T56	14361	0	0	0
T72	28642	26	0	0
T147	0	4	0	0
T150	0	46	0	0
T160	0	42	0	0
T182	0	24	0	0
T183	0	30	0	0
T184	0	16	0	0
T185	0	24	0	0
T186	0	22	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2848	0	0
T52	41083	62	0	0
T56	14361	0	0	0
T72	28642	20	0	0
T147	0	1	0	0
T150	0	11	0	0
T152	0	26	0	0
T160	0	53	0	0
T182	0	19	0	0
T183	0	23	0	0
T184	0	14	0	0
T185	0	14	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2825	0	0
T52	41083	49	0	0
T56	14361	0	0	0
T72	28642	19	0	0
T147	0	5	0	0
T150	0	29	0	0
T152	0	3	0	0
T160	0	41	0	0
T182	0	69	0	0
T183	0	31	0	0
T184	0	10	0	0
T185	0	19	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2960	0	0
T52	41083	73	0	0
T56	14361	0	0	0
T72	28642	23	0	0
T147	0	1	0	0
T150	0	103	0	0
T152	0	13	0	0
T160	0	46	0	0
T182	0	23	0	0
T183	0	43	0	0
T184	0	20	0	0
T185	0	33	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2960	0	0
T52	41083	60	0	0
T56	14361	0	0	0
T72	28642	2	0	0
T147	0	1	0	0
T150	0	73	0	0
T152	0	46	0	0
T160	0	45	0	0
T182	0	33	0	0
T183	0	21	0	0
T184	0	6	0	0
T185	0	32	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2913	0	0
T52	41083	62	0	0
T56	14361	0	0	0
T72	28642	23	0	0
T147	0	7	0	0
T150	0	26	0	0
T152	0	24	0	0
T160	0	66	0	0
T182	0	26	0	0
T183	0	26	0	0
T184	0	23	0	0
T185	0	39	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	3382	0	0
T39	9326	0	0	0
T52	0	77	0	0
T61	94477	0	0	0
T72	0	22	0	0
T100	15368	0	0	0
T182	0	84	0	0
T183	0	65	0	0
T184	0	20	0	0
T194	51884	28	0	0
T195	0	35	0	0
T196	0	15	0	0
T197	0	8	0	0
T198	0	54	0	0
T199	6275	0	0	0
T200	39638	0	0	0
T201	172773	0	0	0
T202	3409	0	0	0
T203	61604	0	0	0
T204	3735	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	3050	0	0
T52	41083	37	0	0
T56	14361	0	0	0
T72	28642	15	0	0
T147	0	9	0	0
T150	0	37	0	0
T152	0	28	0	0
T160	0	45	0	0
T182	0	45	0	0
T183	0	38	0	0
T184	0	16	0	0
T185	0	43	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	3074	0	0
T52	41083	66	0	0
T56	14361	0	0	0
T72	28642	41	0	0
T150	0	67	0	0
T152	0	6	0	0
T160	0	55	0	0
T182	0	51	0	0
T183	0	57	0	0
T184	0	38	0	0
T185	0	21	0	0
T186	0	18	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2784	0	0
T52	41083	41	0	0
T56	14361	0	0	0
T72	28642	8	0	0
T147	0	1	0	0
T150	0	48	0	0
T152	0	4	0	0
T160	0	41	0	0
T182	0	40	0	0
T183	0	28	0	0
T184	0	16	0	0
T185	0	33	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2840	0	0
T52	41083	56	0	0
T56	14361	0	0	0
T72	28642	6	0	0
T147	0	10	0	0
T150	0	22	0	0
T152	0	25	0	0
T160	0	41	0	0
T182	0	18	0	0
T183	0	39	0	0
T184	0	32	0	0
T185	0	32	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2740	0	0
T52	41083	76	0	0
T56	14361	0	0	0
T72	28642	10	0	0
T150	0	44	0	0
T152	0	50	0	0
T160	0	45	0	0
T182	0	26	0	0
T183	0	18	0	0
T184	0	17	0	0
T185	0	32	0	0
T186	0	13	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2790	0	0
T52	41083	50	0	0
T56	14361	0	0	0
T72	28642	33	0	0
T150	0	54	0	0
T152	0	6	0	0
T160	0	54	0	0
T182	0	30	0	0
T183	0	47	0	0
T184	0	10	0	0
T185	0	25	0	0
T186	0	42	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2893	0	0
T52	41083	47	0	0
T56	14361	0	0	0
T72	28642	21	0	0
T150	0	54	0	0
T152	0	48	0	0
T160	0	57	0	0
T182	0	37	0	0
T183	0	18	0	0
T184	0	12	0	0
T185	0	24	0	0
T186	0	13	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2937	0	0
T52	41083	91	0	0
T56	14361	0	0	0
T72	28642	21	0	0
T147	0	7	0	0
T150	0	12	0	0
T152	0	3	0	0
T160	0	58	0	0
T182	0	31	0	0
T183	0	45	0	0
T184	0	12	0	0
T185	0	30	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2635	0	0
T52	41083	66	0	0
T56	14361	0	0	0
T72	28642	25	0	0
T150	0	10	0	0
T152	0	1	0	0
T160	0	32	0	0
T182	0	42	0	0
T183	0	31	0	0
T185	0	37	0	0
T186	0	6	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0
T205	0	9	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2784	0	0
T52	41083	45	0	0
T56	14361	0	0	0
T72	28642	8	0	0
T150	0	21	0	0
T152	0	44	0	0
T160	0	36	0	0
T182	0	45	0	0
T183	0	39	0	0
T184	0	7	0	0
T185	0	42	0	0
T186	0	13	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2907	0	0
T52	41083	52	0	0
T56	14361	0	0	0
T72	28642	18	0	0
T150	0	29	0	0
T152	0	37	0	0
T160	0	58	0	0
T182	0	37	0	0
T183	0	39	0	0
T184	0	4	0	0
T185	0	33	0	0
T186	0	14	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2863	0	0
T52	41083	58	0	0
T56	14361	0	0	0
T72	28642	16	0	0
T147	0	9	0	0
T150	0	30	0	0
T152	0	35	0	0
T160	0	34	0	0
T182	0	63	0	0
T183	0	28	0	0
T184	0	9	0	0
T185	0	21	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2895	0	0
T52	41083	54	0	0
T56	14361	0	0	0
T72	28642	25	0	0
T150	0	32	0	0
T152	0	9	0	0
T160	0	50	0	0
T182	0	16	0	0
T183	0	19	0	0
T184	0	12	0	0
T185	0	35	0	0
T186	0	39	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2708	0	0
T52	41083	50	0	0
T56	14361	0	0	0
T72	28642	7	0	0
T147	0	9	0	0
T150	0	44	0	0
T152	0	22	0	0
T160	0	20	0	0
T182	0	39	0	0
T183	0	20	0	0
T184	0	6	0	0
T185	0	26	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	3032	0	0
T52	41083	61	0	0
T56	14361	0	0	0
T72	28642	17	0	0
T147	0	9	0	0
T150	0	57	0	0
T152	0	1	0	0
T160	0	69	0	0
T182	0	30	0	0
T183	0	48	0	0
T184	0	13	0	0
T185	0	15	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2906	0	0
T52	41083	48	0	0
T56	14361	0	0	0
T72	28642	13	0	0
T150	0	27	0	0
T152	0	26	0	0
T160	0	52	0	0
T182	0	39	0	0
T183	0	34	0	0
T184	0	27	0	0
T185	0	16	0	0
T186	0	7	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	3015	0	0
T52	41083	41	0	0
T56	14361	0	0	0
T72	28642	34	0	0
T150	0	55	0	0
T152	0	22	0	0
T160	0	62	0	0
T182	0	16	0	0
T183	0	27	0	0
T184	0	20	0	0
T185	0	34	0	0
T186	0	24	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2875	0	0
T52	41083	56	0	0
T56	14361	0	0	0
T72	28642	16	0	0
T150	0	56	0	0
T152	0	6	0	0
T160	0	50	0	0
T182	0	25	0	0
T183	0	53	0	0
T184	0	20	0	0
T185	0	34	0	0
T186	0	14	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2896	0	0
T52	41083	49	0	0
T56	14361	0	0	0
T72	28642	1	0	0
T150	0	81	0	0
T152	0	14	0	0
T160	0	48	0	0
T182	0	32	0	0
T183	0	53	0	0
T184	0	11	0	0
T185	0	22	0	0
T186	0	4	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	3034	0	0
T52	41083	53	0	0
T56	14361	0	0	0
T72	28642	30	0	0
T147	0	3	0	0
T150	0	55	0	0
T152	0	43	0	0
T160	0	42	0	0
T182	0	34	0	0
T183	0	32	0	0
T184	0	4	0	0
T185	0	38	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2830	0	0
T52	41083	83	0	0
T56	14361	0	0	0
T72	28642	22	0	0
T150	0	7	0	0
T152	0	9	0	0
T160	0	51	0	0
T182	0	26	0	0
T183	0	10	0	0
T184	0	35	0	0
T185	0	22	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0
T205	0	30	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21227055	2788	0	0
T52	41083	57	0	0
T56	14361	0	0	0
T72	28642	36	0	0
T147	0	2	0	0
T150	0	41	0	0
T152	0	8	0	0
T160	0	45	0	0
T182	0	21	0	0
T183	0	37	0	0
T184	0	13	0	0
T185	0	23	0	0
T187	2975	0	0	0
T188	13578	0	0	0
T189	1001	0	0	0
T190	4225	0	0	0
T191	15400	0	0	0
T192	625	0	0	0
T193	3942	0	0	0