Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3525002	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

624550

1

T1

303

T2

226

T3

292

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3730700	1			T1	887		T2	556		T3	5061
values[0x0]	208138	1			T1	125		T2	62		T3	77
values[0x1]	210714	1			T1	143		T2	63		T3	64

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2410237	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1739315

1

T1

563

T2

348

T3

1885

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14148	1			T1	2		T15	2		T4	51
valid_sources[0x01]	13017	1			T1	2		T15	2		T4	1
valid_sources[0x02]	27347	1			T1	6		T15	3		T4	21
valid_sources[0x03]	15519	1			T15	3		T4	4		T5	16
valid_sources[0x04]	12295	1			T1	2		T15	6		T4	2
valid_sources[0x05]	12742	1			T1	5		T15	1		T5	6
valid_sources[0x06]	14720	1			T1	3		T4	7		T5	4
valid_sources[0x07]	17823	1			T1	6		T15	2		T4	4
valid_sources[0x08]	12558	1			T1	4		T15	3		T5	1
valid_sources[0x09]	13080	1			T1	3		T15	4		T4	1
valid_sources[0x0a]	22934	1			T1	3		T4	12		T5	5
valid_sources[0x0b]	12031	1			T1	8		T4	2		T5	8
valid_sources[0x0c]	13973	1			T1	5		T15	1		T4	15
valid_sources[0x0d]	18583	1			T1	6		T15	2		T5	1
valid_sources[0x0e]	21169	1			T1	7		T15	3		T5	12
valid_sources[0x0f]	12890	1			T1	4		T15	5		T4	1
valid_sources[0x10]	13163	1			T1	3		T15	1		T4	2
valid_sources[0x11]	14620	1			T1	6		T15	2		T5	10
valid_sources[0x12]	13682	1			T1	3		T15	5		T4	8
valid_sources[0x13]	12585	1			T15	1		T4	36		T5	6
valid_sources[0x14]	25268	1			T1	6		T4	6		T5	11
valid_sources[0x15]	14802	1			T1	4		T15	3		T4	1
valid_sources[0x16]	21330	1			T1	6		T15	3		T4	13
valid_sources[0x17]	12648	1			T1	6		T15	3		T4	25
valid_sources[0x18]	17340	1			T1	8		T4	4		T5	13
valid_sources[0x19]	13089	1			T1	8		T4	12		T5	4
valid_sources[0x1a]	13089	1			T1	4		T15	1		T4	10
valid_sources[0x1b]	15474	1			T1	7		T15	5		T4	12
valid_sources[0x1c]	14705	1			T1	8		T15	2		T4	5
valid_sources[0x1d]	13118	1			T1	10		T15	2		T4	14
valid_sources[0x1e]	15941	1			T1	6		T15	8		T4	7
valid_sources[0x1f]	21088	1			T1	5		T4	5		T5	9
valid_sources[0x20]	17218	1			T1	7		T15	2		T5	8
valid_sources[0x21]	20458	1			T1	2		T4	8		T5	5
valid_sources[0x22]	13166	1			T1	3		T15	3		T4	28
valid_sources[0x23]	13482	1			T1	3		T15	6		T4	29
valid_sources[0x24]	13095	1			T1	7		T15	2		T4	11
valid_sources[0x25]	14889	1			T1	6		T15	3		T5	11
valid_sources[0x26]	13640	1			T1	2		T15	4		T5	7
valid_sources[0x27]	13171	1			T1	6		T15	1		T4	12
valid_sources[0x28]	12199	1			T1	1		T15	1		T5	11
valid_sources[0x29]	15896	1			T1	5		T15	2		T4	23
valid_sources[0x2a]	13808	1			T1	7		T15	1		T4	25
valid_sources[0x2b]	13782	1			T1	5		T15	1		T4	5
valid_sources[0x2c]	13675	1			T1	9		T4	6		T5	6
valid_sources[0x2d]	13237	1			T1	4		T15	9		T4	3
valid_sources[0x2e]	12614	1			T1	3		T15	1		T4	5
valid_sources[0x2f]	14806	1			T1	5		T4	15		T5	6
valid_sources[0x30]	13823	1			T1	11		T15	4		T5	3
valid_sources[0x31]	17834	1			T1	5		T15	2		T5	8
valid_sources[0x32]	18167	1			T1	4		T15	1		T5	11
valid_sources[0x33]	16232	1			T1	3		T15	1		T4	28
valid_sources[0x34]	12632	1			T1	3		T15	1		T4	3
valid_sources[0x35]	15628	1			T1	2		T15	1		T4	14
valid_sources[0x36]	17929	1			T1	2		T15	1		T5	1
valid_sources[0x37]	12499	1			T1	5		T15	5		T4	7
valid_sources[0x38]	12562	1			T1	2		T15	9		T4	1
valid_sources[0x39]	16552	1			T1	5		T15	1		T4	4
valid_sources[0x3a]	13019	1			T1	3		T15	2		T5	8
valid_sources[0x3b]	14387	1			T1	4		T15	3		T4	30
valid_sources[0x3c]	16507	1			T1	2		T15	5		T4	2
valid_sources[0x3d]	25050	1			T1	8		T15	2		T4	5
valid_sources[0x3e]	15277	1			T1	2		T15	2		T4	17
valid_sources[0x3f]	15340	1			T1	2		T15	3		T4	9
valid_sources[0x40]	20402	1			T1	3		T15	1		T4	17
valid_sources[0x41]	14691	1			T1	2		T15	6		T4	2
valid_sources[0x42]	15318	1			T1	3		T15	4		T4	6
valid_sources[0x43]	15805	1			T1	3		T15	2		T5	5
valid_sources[0x44]	13230	1			T1	4		T15	8		T4	11
valid_sources[0x45]	12871	1			T1	6		T15	2		T4	10
valid_sources[0x46]	13041	1			T1	8		T15	5		T5	12
valid_sources[0x47]	16228	1			T1	6		T15	3		T5	11
valid_sources[0x48]	12517	1			T1	5		T15	2		T4	5
valid_sources[0x49]	17624	1			T1	5		T15	5		T4	22
valid_sources[0x4a]	12783	1			T1	4		T4	13		T5	10
valid_sources[0x4b]	29080	1			T1	1		T15	2		T4	1
valid_sources[0x4c]	14065	1			T1	1		T15	1		T4	4
valid_sources[0x4d]	39330	1			T1	2		T15	1		T4	1
valid_sources[0x4e]	13781	1			T1	4		T15	4		T4	1
valid_sources[0x4f]	13348	1			T1	2		T15	6		T4	4
valid_sources[0x50]	47141	1			T1	2		T5	11		T16	2
valid_sources[0x51]	14186	1			T1	8		T15	5		T5	7
valid_sources[0x52]	13154	1			T1	4		T15	1		T5	12
valid_sources[0x53]	13304	1			T1	6		T4	1		T5	2
valid_sources[0x54]	12258	1			T1	3		T15	4		T4	3
valid_sources[0x55]	34420	1			T1	6		T15	2		T4	2
valid_sources[0x56]	20764	1			T1	3		T15	1		T4	16
valid_sources[0x57]	12860	1			T1	3		T15	1		T4	3
valid_sources[0x58]	12511	1			T1	4		T15	9		T5	3
valid_sources[0x59]	19612	1			T1	7		T15	1		T4	18
valid_sources[0x5a]	12588	1			T1	6		T15	4		T4	9
valid_sources[0x5b]	15040	1			T1	5		T4	6		T5	2
valid_sources[0x5c]	14414	1			T1	8		T15	2		T4	14
valid_sources[0x5d]	47595	1			T1	6		T15	6		T4	22
valid_sources[0x5e]	29599	1			T1	6		T15	5		T4	4
valid_sources[0x5f]	14371	1			T1	6		T15	2		T5	2
valid_sources[0x60]	14512	1			T1	1		T15	6		T4	16
valid_sources[0x61]	15502	1			T1	2		T15	2		T4	11
valid_sources[0x62]	14071	1			T1	3		T15	2		T5	1
valid_sources[0x63]	17791	1			T1	3		T15	8		T4	11
valid_sources[0x64]	15892	1			T1	8		T5	7		T16	4
valid_sources[0x65]	14668	1			T1	3		T15	2		T4	11
valid_sources[0x66]	13594	1			T1	5		T15	1		T4	43
valid_sources[0x67]	13670	1			T1	1		T15	2		T5	2
valid_sources[0x68]	12361	1			T1	3		T15	1		T4	3
valid_sources[0x69]	14013	1			T1	4		T15	2		T5	16
valid_sources[0x6a]	22253	1			T1	5		T15	6		T4	36
valid_sources[0x6b]	14340	1			T1	4		T15	4		T4	2
valid_sources[0x6c]	13069	1			T1	5		T15	3		T4	16
valid_sources[0x6d]	29949	1			T1	3		T15	5		T5	1
valid_sources[0x6e]	12794	1			T1	3		T15	2		T5	13
valid_sources[0x6f]	12842	1			T1	4		T15	2		T4	5
valid_sources[0x70]	15229	1			T1	2		T15	4		T4	28
valid_sources[0x71]	12615	1			T1	5		T15	4		T4	7
valid_sources[0x72]	12544	1			T1	2		T15	5		T4	7
valid_sources[0x73]	12830	1			T1	2		T15	3		T4	9
valid_sources[0x74]	26170	1			T1	4		T15	1		T4	16
valid_sources[0x75]	13984	1			T1	2		T15	1		T4	7
valid_sources[0x76]	14998	1			T1	2		T15	2		T5	11
valid_sources[0x77]	32623	1			T1	4		T15	3		T4	11
valid_sources[0x78]	22513	1			T1	1		T15	1		T4	8
valid_sources[0x79]	12141	1			T1	3		T15	3		T4	38
valid_sources[0x7a]	12957	1			T1	3		T15	3		T4	17
valid_sources[0x7b]	12932	1			T1	6		T15	3		T4	17
valid_sources[0x7c]	16165	1			T1	9		T2	681		T15	5
valid_sources[0x7d]	16432	1			T1	5		T15	2		T5	2
valid_sources[0x7e]	14860	1			T1	4		T15	3		T5	6
valid_sources[0x7f]	13187	1			T1	5		T15	2		T5	13
valid_sources[0x80]	12990	1			T1	5		T15	4		T4	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

340337

1

T1

150

T2

178

T3

255

values[0x0]

all_enables

biggest_size

149760

1

T1

74

T2

37

T3

28

values[0x1]

all_enables

biggest_size

134453

1

T1

79

T2

11

T3

9