Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
25622856 |
25461854 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25622856 |
25461854 |
0 |
0 |
T1 |
14122 |
14072 |
0 |
0 |
T2 |
7365 |
7267 |
0 |
0 |
T3 |
52579 |
52489 |
0 |
0 |
T4 |
5112 |
5052 |
0 |
0 |
T5 |
6332 |
6251 |
0 |
0 |
T15 |
2401 |
2325 |
0 |
0 |
T16 |
8774 |
8693 |
0 |
0 |
T17 |
42793 |
42433 |
0 |
0 |
T18 |
1654 |
1581 |
0 |
0 |
T19 |
258126 |
258044 |
0 |
0 |