Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	27375874	17440	0	0
attest_sw_binding_0_rd_A	27375874	2696	0	0
attest_sw_binding_1_rd_A	27375874	2556	0	0
attest_sw_binding_2_rd_A	27375874	2631	0	0
attest_sw_binding_3_rd_A	27375874	2641	0	0
attest_sw_binding_4_rd_A	27375874	2567	0	0
attest_sw_binding_5_rd_A	27375874	2768	0	0
attest_sw_binding_6_rd_A	27375874	2507	0	0
attest_sw_binding_7_rd_A	27375874	2509	0	0
intr_enable_rd_A	27375874	3337	0	0
key_version_rd_A	27375874	2442	0	0
max_creator_key_ver_regwen_rd_A	27375874	2656	0	0
max_owner_int_key_ver_regwen_rd_A	27375874	2630	0	0
max_owner_key_ver_regwen_rd_A	27375874	2547	0	0
reseed_interval_regwen_rd_A	27375874	2534	0	0
salt_0_rd_A	27375874	2672	0	0
salt_1_rd_A	27375874	2643	0	0
salt_2_rd_A	27375874	2659	0	0
salt_3_rd_A	27375874	2613	0	0
salt_4_rd_A	27375874	2528	0	0
salt_5_rd_A	27375874	2640	0	0
salt_6_rd_A	27375874	2640	0	0
salt_7_rd_A	27375874	2518	0	0
sealing_sw_binding_0_rd_A	27375874	2699	0	0
sealing_sw_binding_1_rd_A	27375874	2709	0	0
sealing_sw_binding_2_rd_A	27375874	2514	0	0
sealing_sw_binding_3_rd_A	27375874	2559	0	0
sealing_sw_binding_4_rd_A	27375874	2508	0	0
sealing_sw_binding_5_rd_A	27375874	2531	0	0
sealing_sw_binding_6_rd_A	27375874	2643	0	0
sealing_sw_binding_7_rd_A	27375874	2501	0	0
sideload_clear_rd_A	27375874	2624	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	17440	0	0
T17	42793	44	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T46	0	880	0	0
T71	0	78	0	0
T72	0	533	0	0
T84	0	534	0	0
T98	11381	0	0	0
T113	0	418	0	0
T133	0	173	0	0
T134	0	29	0	0
T135	0	407	0	0
T136	7636	0	0	0
T138	0	1131	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2696	0	0
T17	42793	46	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	28	0	0
T86	0	33	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	13	0	0
T191	0	53	0	0
T192	0	41	0	0
T193	0	11	0	0
T194	0	20	0	0
T195	0	49	0	0
T196	0	13	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2556	0	0
T17	42793	46	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	15	0	0
T86	0	33	0	0
T98	11381	0	0	0
T128	0	20	0	0
T136	7636	0	0	0
T191	0	33	0	0
T192	0	18	0	0
T193	0	21	0	0
T194	0	26	0	0
T195	0	63	0	0
T196	0	11	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2631	0	0
T17	42793	45	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	21	0	0
T86	0	37	0	0
T98	11381	0	0	0
T128	0	29	0	0
T136	7636	0	0	0
T191	0	48	0	0
T192	0	43	0	0
T193	0	10	0	0
T194	0	7	0	0
T195	0	54	0	0
T196	0	5	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2641	0	0
T17	42793	55	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	18	0	0
T86	0	52	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	12	0	0
T191	0	64	0	0
T192	0	22	0	0
T193	0	31	0	0
T194	0	8	0	0
T195	0	52	0	0
T196	0	9	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2567	0	0
T17	42793	76	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	37	0	0
T86	0	25	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	1	0	0
T191	0	12	0	0
T192	0	22	0	0
T193	0	14	0	0
T194	0	8	0	0
T195	0	81	0	0
T196	0	9	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2768	0	0
T17	42793	80	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	29	0	0
T86	0	41	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	3	0	0
T191	0	36	0	0
T192	0	24	0	0
T193	0	25	0	0
T194	0	16	0	0
T195	0	77	0	0
T196	0	7	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2507	0	0
T17	42793	51	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	26	0	0
T86	0	31	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	7	0	0
T191	0	21	0	0
T192	0	30	0	0
T193	0	19	0	0
T194	0	19	0	0
T195	0	55	0	0
T196	0	12	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2509	0	0
T17	42793	55	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	6	0	0
T86	0	22	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	3	0	0
T191	0	26	0	0
T192	0	28	0	0
T193	0	13	0	0
T194	0	12	0	0
T195	0	52	0	0
T196	0	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	3337	0	0
T17	42793	43	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T59	0	73	0	0
T71	0	40	0	0
T86	0	27	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T191	0	31	0	0
T197	0	31	0	0
T198	0	49	0	0
T199	0	36	0	0
T200	0	6	0	0
T201	0	15	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2442	0	0
T17	42793	55	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	20	0	0
T86	0	45	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	1	0	0
T191	0	25	0	0
T192	0	13	0	0
T193	0	14	0	0
T194	0	20	0	0
T195	0	62	0	0
T196	0	14	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2656	0	0
T17	42793	64	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	33	0	0
T86	0	53	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	5	0	0
T191	0	12	0	0
T192	0	33	0	0
T193	0	7	0	0
T194	0	7	0	0
T195	0	63	0	0
T196	0	5	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2630	0	0
T17	42793	55	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	41	0	0
T86	0	29	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	6	0	0
T191	0	43	0	0
T192	0	40	0	0
T193	0	21	0	0
T194	0	12	0	0
T195	0	51	0	0
T196	0	5	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2547	0	0
T17	42793	60	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	19	0	0
T86	0	38	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	2	0	0
T191	0	35	0	0
T192	0	18	0	0
T193	0	21	0	0
T194	0	10	0	0
T195	0	63	0	0
T196	0	6	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2534	0	0
T17	42793	46	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	32	0	0
T86	0	37	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	8	0	0
T191	0	28	0	0
T192	0	34	0	0
T193	0	4	0	0
T194	0	12	0	0
T195	0	47	0	0
T196	0	16	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2672	0	0
T17	42793	44	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	25	0	0
T86	0	23	0	0
T98	11381	0	0	0
T128	0	20	0	0
T136	7636	0	0	0
T191	0	31	0	0
T192	0	50	0	0
T193	0	25	0	0
T194	0	15	0	0
T195	0	77	0	0
T196	0	19	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2643	0	0
T17	42793	52	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	19	0	0
T86	0	34	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	9	0	0
T191	0	53	0	0
T192	0	31	0	0
T193	0	11	0	0
T194	0	6	0	0
T195	0	58	0	0
T196	0	11	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2659	0	0
T17	42793	46	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	24	0	0
T86	0	73	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	6	0	0
T191	0	46	0	0
T192	0	11	0	0
T193	0	33	0	0
T194	0	8	0	0
T195	0	49	0	0
T196	0	1	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2613	0	0
T17	42793	51	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	42	0	0
T86	0	29	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T191	0	46	0	0
T192	0	24	0	0
T193	0	12	0	0
T194	0	8	0	0
T195	0	36	0	0
T196	0	11	0	0
T202	0	3	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2528	0	0
T17	42793	32	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	8	0	0
T86	0	27	0	0
T98	11381	0	0	0
T128	0	12	0	0
T136	7636	0	0	0
T191	0	19	0	0
T192	0	14	0	0
T193	0	8	0	0
T194	0	14	0	0
T195	0	44	0	0
T196	0	8	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2640	0	0
T17	42793	79	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	39	0	0
T86	0	22	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	11	0	0
T191	0	22	0	0
T192	0	23	0	0
T193	0	8	0	0
T194	0	16	0	0
T195	0	68	0	0
T196	0	15	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2640	0	0
T17	42793	44	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	39	0	0
T86	0	32	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	7	0	0
T191	0	24	0	0
T192	0	17	0	0
T193	0	34	0	0
T194	0	10	0	0
T195	0	36	0	0
T196	0	5	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2518	0	0
T17	42793	32	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	14	0	0
T86	0	25	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	6	0	0
T191	0	51	0	0
T192	0	41	0	0
T193	0	18	0	0
T194	0	14	0	0
T195	0	55	0	0
T196	0	15	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2699	0	0
T17	42793	61	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	30	0	0
T86	0	45	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T191	0	30	0	0
T192	0	23	0	0
T193	0	30	0	0
T194	0	17	0	0
T195	0	65	0	0
T196	0	11	0	0
T203	0	2	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2709	0	0
T17	42793	74	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	27	0	0
T86	0	27	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	14	0	0
T191	0	46	0	0
T192	0	41	0	0
T193	0	34	0	0
T194	0	13	0	0
T195	0	46	0	0
T196	0	20	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2514	0	0
T17	42793	38	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	15	0	0
T86	0	19	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	1	0	0
T191	0	21	0	0
T192	0	10	0	0
T193	0	25	0	0
T194	0	6	0	0
T195	0	78	0	0
T196	0	7	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2559	0	0
T17	42793	52	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	37	0	0
T86	0	30	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	2	0	0
T191	0	43	0	0
T192	0	12	0	0
T193	0	13	0	0
T194	0	18	0	0
T195	0	51	0	0
T196	0	7	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2508	0	0
T17	42793	38	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	16	0	0
T86	0	30	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	5	0	0
T191	0	40	0	0
T192	0	11	0	0
T193	0	22	0	0
T194	0	4	0	0
T195	0	47	0	0
T196	0	13	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2531	0	0
T17	42793	67	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	48	0	0
T86	0	31	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	4	0	0
T191	0	30	0	0
T192	0	4	0	0
T193	0	4	0	0
T194	0	8	0	0
T195	0	39	0	0
T196	0	4	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2643	0	0
T17	42793	45	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	24	0	0
T86	0	32	0	0
T98	11381	0	0	0
T128	0	24	0	0
T136	7636	0	0	0
T190	0	12	0	0
T191	0	34	0	0
T192	0	34	0	0
T193	0	24	0	0
T195	0	71	0	0
T196	0	12	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2501	0	0
T17	42793	57	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	33	0	0
T86	0	29	0	0
T98	11381	0	0	0
T136	7636	0	0	0
T190	0	10	0	0
T191	0	22	0	0
T192	0	32	0	0
T193	0	14	0	0
T194	0	18	0	0
T195	0	56	0	0
T196	0	4	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27375874	2624	0	0
T17	42793	57	0	0
T18	1654	0	0	0
T19	258126	0	0	0
T24	12887	0	0	0
T35	13147	0	0	0
T36	9496	0	0	0
T37	11160	0	0	0
T45	9983	0	0	0
T71	0	18	0	0
T86	0	31	0	0
T98	11381	0	0	0
T110	0	4	0	0
T136	7636	0	0	0
T190	0	5	0	0
T191	0	30	0	0
T192	0	36	0	0
T193	0	5	0	0
T194	0	10	0	0
T195	0	65	0	0