Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2958012	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

637344

1

T1

462

T2

2764

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3169532	1			T1	1231		T2	3862		T3	2962
values[0x0]	211349	1			T1	122		T2	862		T3	15
values[0x1]	214475	1			T1	129		T2	863		T3	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2032651	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1562705

1

T1

746

T2

3464

T3

987

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12806	1			T1	4		T2	13		T11	7
valid_sources[0x01]	11408	1			T1	5		T2	22		T11	8
valid_sources[0x02]	11776	1			T2	31		T11	11		T14	6
valid_sources[0x03]	12681	1			T1	11		T2	15		T11	11
valid_sources[0x04]	12819	1			T1	6		T2	17		T11	11
valid_sources[0x05]	12397	1			T1	5		T2	17		T11	18
valid_sources[0x06]	12274	1			T1	5		T2	16		T11	5
valid_sources[0x07]	21823	1			T1	7		T2	8		T11	6
valid_sources[0x08]	11513	1			T1	7		T2	24		T11	1
valid_sources[0x09]	12702	1			T1	10		T2	13		T11	7
valid_sources[0x0a]	17345	1			T1	4		T2	23		T11	7
valid_sources[0x0b]	16035	1			T1	5		T2	30		T11	7
valid_sources[0x0c]	12502	1			T1	7		T2	25		T11	2
valid_sources[0x0d]	11652	1			T1	5		T2	25		T14	3
valid_sources[0x0e]	11578	1			T1	6		T2	17		T11	13
valid_sources[0x0f]	17506	1			T1	1		T2	27		T11	8
valid_sources[0x10]	13468	1			T1	6		T2	18		T11	4
valid_sources[0x11]	12210	1			T1	3		T2	17		T11	4
valid_sources[0x12]	12643	1			T1	3		T2	33		T11	5
valid_sources[0x13]	13028	1			T1	5		T2	25		T11	3
valid_sources[0x14]	13508	1			T1	10		T2	9		T11	8
valid_sources[0x15]	14244	1			T1	8		T2	12		T11	3
valid_sources[0x16]	11754	1			T1	8		T2	19		T11	3
valid_sources[0x17]	11816	1			T1	5		T2	17		T11	8
valid_sources[0x18]	13092	1			T1	9		T2	31		T11	5
valid_sources[0x19]	16599	1			T1	12		T2	25		T11	9
valid_sources[0x1a]	16587	1			T1	5		T2	23		T11	9
valid_sources[0x1b]	12534	1			T1	9		T2	13		T11	7
valid_sources[0x1c]	11412	1			T1	2		T2	12		T11	9
valid_sources[0x1d]	11645	1			T1	2		T2	11		T11	12
valid_sources[0x1e]	41062	1			T1	5		T2	18		T11	5
valid_sources[0x1f]	11570	1			T1	5		T2	29		T11	2
valid_sources[0x20]	13481	1			T1	7		T2	16		T11	3
valid_sources[0x21]	15100	1			T1	9		T2	16		T11	4
valid_sources[0x22]	23662	1			T2	21		T11	13		T14	1
valid_sources[0x23]	11932	1			T1	6		T2	17		T11	7
valid_sources[0x24]	14759	1			T1	8		T2	36		T3	2997
valid_sources[0x25]	40550	1			T1	4		T2	21		T11	7
valid_sources[0x26]	13118	1			T1	6		T2	15		T11	9
valid_sources[0x27]	13497	1			T1	5		T2	26		T11	15
valid_sources[0x28]	18548	1			T1	2		T2	41		T11	2
valid_sources[0x29]	14206	1			T1	2		T2	32		T11	5
valid_sources[0x2a]	17888	1			T1	8		T2	32		T11	5
valid_sources[0x2b]	11744	1			T1	10		T2	20		T11	4
valid_sources[0x2c]	12814	1			T1	7		T2	15		T11	6
valid_sources[0x2d]	11313	1			T1	5		T2	22		T11	5
valid_sources[0x2e]	16729	1			T1	4		T2	19		T11	5
valid_sources[0x2f]	14960	1			T1	5		T2	28		T11	4
valid_sources[0x30]	11552	1			T1	3		T2	25		T11	1
valid_sources[0x31]	11844	1			T1	4		T2	14		T11	3
valid_sources[0x32]	11796	1			T1	10		T2	17		T11	16
valid_sources[0x33]	11671	1			T1	7		T2	32		T11	6
valid_sources[0x34]	12223	1			T1	3		T2	18		T11	1
valid_sources[0x35]	14757	1			T1	4		T2	25		T11	13
valid_sources[0x36]	15298	1			T1	6		T2	21		T11	6
valid_sources[0x37]	15685	1			T1	7		T2	37		T11	10
valid_sources[0x38]	13403	1			T1	5		T2	18		T11	1
valid_sources[0x39]	14445	1			T1	7		T2	17		T11	5
valid_sources[0x3a]	27109	1			T1	4		T2	26		T11	8
valid_sources[0x3b]	13784	1			T1	1		T2	27		T11	13
valid_sources[0x3c]	13073	1			T1	3		T2	13		T11	9
valid_sources[0x3d]	12194	1			T1	7		T2	9		T11	11
valid_sources[0x3e]	11796	1			T1	3		T2	17		T11	13
valid_sources[0x3f]	11903	1			T1	12		T2	33		T11	8
valid_sources[0x40]	11799	1			T1	7		T2	24		T11	3
valid_sources[0x41]	13764	1			T1	6		T2	23		T11	3
valid_sources[0x42]	14810	1			T1	10		T2	15		T11	4
valid_sources[0x43]	12600	1			T1	3		T2	19		T11	4
valid_sources[0x44]	11943	1			T1	2		T2	21		T11	14
valid_sources[0x45]	11273	1			T1	7		T2	27		T11	8
valid_sources[0x46]	13799	1			T1	12		T2	21		T11	4
valid_sources[0x47]	11737	1			T1	5		T2	24		T11	4
valid_sources[0x48]	12831	1			T1	5		T2	35		T11	3
valid_sources[0x49]	11845	1			T1	4		T2	31		T11	5
valid_sources[0x4a]	11526	1			T1	10		T2	26		T11	2
valid_sources[0x4b]	14817	1			T1	6		T2	18		T11	6
valid_sources[0x4c]	14820	1			T1	2		T2	6		T11	2
valid_sources[0x4d]	19392	1			T1	9		T2	28		T11	6
valid_sources[0x4e]	29006	1			T1	1		T2	24		T11	14
valid_sources[0x4f]	15723	1			T1	6		T2	27		T14	2
valid_sources[0x50]	12791	1			T1	4		T2	26		T11	8
valid_sources[0x51]	11979	1			T1	7		T2	16		T11	5
valid_sources[0x52]	13208	1			T1	6		T2	22		T11	4
valid_sources[0x53]	12616	1			T1	1		T2	16		T11	4
valid_sources[0x54]	13024	1			T1	4		T2	22		T11	10
valid_sources[0x55]	14498	1			T1	9		T2	25		T11	5
valid_sources[0x56]	58618	1			T1	11		T2	24		T11	11
valid_sources[0x57]	11792	1			T1	1		T2	45		T11	3
valid_sources[0x58]	12255	1			T1	4		T2	20		T11	5
valid_sources[0x59]	13441	1			T1	11		T2	29		T11	7
valid_sources[0x5a]	11596	1			T1	12		T2	24		T11	1
valid_sources[0x5b]	15788	1			T1	7		T2	21		T11	11
valid_sources[0x5c]	11753	1			T1	9		T2	50		T11	7
valid_sources[0x5d]	11610	1			T1	6		T2	29		T11	8
valid_sources[0x5e]	12951	1			T1	3		T2	17		T11	13
valid_sources[0x5f]	11534	1			T1	8		T2	24		T11	2
valid_sources[0x60]	15027	1			T1	7		T2	18		T11	4
valid_sources[0x61]	16586	1			T1	5		T2	26		T11	10
valid_sources[0x62]	12776	1			T1	7		T2	30		T11	5
valid_sources[0x63]	11102	1			T1	7		T2	18		T11	5
valid_sources[0x64]	12235	1			T1	3		T2	21		T11	13
valid_sources[0x65]	11754	1			T1	17		T2	22		T11	10
valid_sources[0x66]	12271	1			T1	2		T2	17		T11	10
valid_sources[0x67]	12212	1			T1	5		T2	17		T11	11
valid_sources[0x68]	14185	1			T1	8		T2	21		T11	6
valid_sources[0x69]	12089	1			T1	7		T2	24		T11	4
valid_sources[0x6a]	11561	1			T1	2		T2	22		T11	2
valid_sources[0x6b]	11609	1			T1	7		T2	37		T11	2
valid_sources[0x6c]	12828	1			T1	6		T2	13		T11	13
valid_sources[0x6d]	13933	1			T1	4		T2	23		T11	10
valid_sources[0x6e]	11559	1			T1	4		T2	12		T11	5
valid_sources[0x6f]	12544	1			T1	2		T2	28		T11	10
valid_sources[0x70]	11651	1			T1	3		T2	24		T11	5
valid_sources[0x71]	11177	1			T1	1		T2	10		T11	2
valid_sources[0x72]	13225	1			T1	4		T2	21		T11	10
valid_sources[0x73]	11420	1			T1	6		T2	19		T11	3
valid_sources[0x74]	11350	1			T1	6		T2	14		T11	6
valid_sources[0x75]	11669	1			T1	2		T2	22		T11	8
valid_sources[0x76]	13715	1			T1	8		T2	24		T11	7
valid_sources[0x77]	13185	1			T1	10		T2	23		T11	9
valid_sources[0x78]	12871	1			T1	11		T2	22		T11	7
valid_sources[0x79]	11177	1			T1	6		T2	28		T11	4
valid_sources[0x7a]	11620	1			T1	4		T2	23		T11	5
valid_sources[0x7b]	12331	1			T1	6		T2	31		T11	12
valid_sources[0x7c]	11602	1			T1	1		T2	18		T11	4
valid_sources[0x7d]	13020	1			T1	4		T2	20		T11	1
valid_sources[0x7e]	12661	1			T1	2		T2	25		T11	1
valid_sources[0x7f]	12611	1			T1	12		T2	24		T11	2
valid_sources[0x80]	11923	1			T1	6		T2	15		T11	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

345550

1

T1

317

T2

1533

T3

8

values[0x0]

all_enables

biggest_size

153167

1

T1

79

T2

658

T3

5

values[0x1]

all_enables

biggest_size

138627

1

T1

66

T2

573

T3

3