Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
21373576 |
21221853 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21373576 |
21221853 |
0 |
0 |
T1 |
14013 |
13946 |
0 |
0 |
T2 |
42753 |
42630 |
0 |
0 |
T3 |
41248 |
41100 |
0 |
0 |
T11 |
10510 |
10452 |
0 |
0 |
T12 |
85053 |
84962 |
0 |
0 |
T13 |
5234 |
5184 |
0 |
0 |
T14 |
3515 |
3458 |
0 |
0 |
T15 |
57365 |
57295 |
0 |
0 |
T16 |
18391 |
18327 |
0 |
0 |
T17 |
16251 |
16193 |
0 |
0 |