SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_lc_keymgr_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 885 | 885 | 0 | 0 |
OutputsKnown_A | 21373576 | 21221853 | 0 | 0 |
gen_flops.OutputDelay_A | 21373576 | 21215136 | 0 | 2655 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 885 | 885 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 21373576 | 21221853 | 0 | 0 |
T1 | 14013 | 13946 | 0 | 0 |
T2 | 42753 | 42630 | 0 | 0 |
T3 | 41248 | 41100 | 0 | 0 |
T11 | 10510 | 10452 | 0 | 0 |
T12 | 85053 | 84962 | 0 | 0 |
T13 | 5234 | 5184 | 0 | 0 |
T14 | 3515 | 3458 | 0 | 0 |
T15 | 57365 | 57295 | 0 | 0 |
T16 | 18391 | 18327 | 0 | 0 |
T17 | 16251 | 16193 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 21373576 | 21215136 | 0 | 2655 |
T1 | 14013 | 13943 | 0 | 3 |
T2 | 42753 | 42597 | 0 | 3 |
T3 | 41248 | 41094 | 0 | 3 |
T11 | 10510 | 10449 | 0 | 3 |
T12 | 85053 | 84959 | 0 | 3 |
T13 | 5234 | 5181 | 0 | 3 |
T14 | 3515 | 3455 | 0 | 3 |
T15 | 57365 | 57292 | 0 | 3 |
T16 | 18391 | 18324 | 0 | 3 |
T17 | 16251 | 16190 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |