Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23183422	15827	0	0
attest_sw_binding_0_rd_A	23183422	2550	0	0
attest_sw_binding_1_rd_A	23183422	2322	0	0
attest_sw_binding_2_rd_A	23183422	2447	0	0
attest_sw_binding_3_rd_A	23183422	2426	0	0
attest_sw_binding_4_rd_A	23183422	2564	0	0
attest_sw_binding_5_rd_A	23183422	2401	0	0
attest_sw_binding_6_rd_A	23183422	2510	0	0
attest_sw_binding_7_rd_A	23183422	2623	0	0
intr_enable_rd_A	23183422	3008	0	0
key_version_rd_A	23183422	2295	0	0
max_creator_key_ver_regwen_rd_A	23183422	2568	0	0
max_owner_int_key_ver_regwen_rd_A	23183422	2560	0	0
max_owner_key_ver_regwen_rd_A	23183422	2343	0	0
reseed_interval_regwen_rd_A	23183422	2529	0	0
salt_0_rd_A	23183422	2397	0	0
salt_1_rd_A	23183422	2732	0	0
salt_2_rd_A	23183422	2506	0	0
salt_3_rd_A	23183422	2418	0	0
salt_4_rd_A	23183422	2252	0	0
salt_5_rd_A	23183422	2534	0	0
salt_6_rd_A	23183422	2383	0	0
salt_7_rd_A	23183422	2473	0	0
sealing_sw_binding_0_rd_A	23183422	2542	0	0
sealing_sw_binding_1_rd_A	23183422	2261	0	0
sealing_sw_binding_2_rd_A	23183422	2474	0	0
sealing_sw_binding_3_rd_A	23183422	2475	0	0
sealing_sw_binding_4_rd_A	23183422	2570	0	0
sealing_sw_binding_5_rd_A	23183422	2524	0	0
sealing_sw_binding_6_rd_A	23183422	2471	0	0
sealing_sw_binding_7_rd_A	23183422	2475	0	0
sideload_clear_rd_A	23183422	2455	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	15827	0	0
T2	42753	49	0	0
T3	41248	0	0	0
T11	10510	0	0	0
T12	85053	0	0	0
T13	5234	0	0	0
T14	3515	0	0	0
T15	57365	0	0	0
T16	18391	0	0	0
T17	16251	0	0	0
T33	3029	0	0	0
T46	0	680	0	0
T60	0	377	0	0
T63	0	1168	0	0
T76	0	209	0	0
T79	0	633	0	0
T105	0	196	0	0
T126	0	628	0	0
T127	0	46	0	0
T128	0	40	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2550	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	10	0	0
T76	0	26	0	0
T92	11388	0	0	0
T127	29009	34	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	23	0	0
T180	0	32	0	0
T181	0	52	0	0
T182	0	25	0	0
T183	0	26	0	0
T184	0	17	0	0
T185	0	34	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2322	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	10	0	0
T76	0	28	0	0
T92	11388	0	0	0
T127	29009	9	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	32	0	0
T180	0	29	0	0
T181	0	38	0	0
T182	0	24	0	0
T183	0	23	0	0
T184	0	10	0	0
T185	0	15	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2447	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	21	0	0
T76	0	27	0	0
T92	11388	0	0	0
T127	29009	35	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	28	0	0
T180	0	42	0	0
T181	0	53	0	0
T182	0	30	0	0
T183	0	6	0	0
T184	0	12	0	0
T185	0	11	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2426	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	7	0	0
T76	0	42	0	0
T92	11388	0	0	0
T127	29009	40	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	36	0	0
T180	0	36	0	0
T181	0	55	0	0
T182	0	23	0	0
T183	0	29	0	0
T184	0	16	0	0
T185	0	27	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2564	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	15	0	0
T76	0	20	0	0
T92	11388	0	0	0
T127	29009	20	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	42	0	0
T180	0	25	0	0
T181	0	80	0	0
T182	0	32	0	0
T183	0	46	0	0
T184	0	7	0	0
T185	0	29	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2401	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	18	0	0
T76	0	43	0	0
T92	11388	0	0	0
T127	29009	23	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	29	0	0
T180	0	30	0	0
T181	0	71	0	0
T182	0	31	0	0
T183	0	30	0	0
T184	0	6	0	0
T185	0	37	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2510	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	4	0	0
T76	0	25	0	0
T92	11388	0	0	0
T127	29009	22	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	32	0	0
T180	0	16	0	0
T181	0	56	0	0
T182	0	24	0	0
T183	0	28	0	0
T184	0	8	0	0
T185	0	27	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2623	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	12	0	0
T76	0	10	0	0
T92	11388	0	0	0
T127	29009	13	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	27	0	0
T180	0	52	0	0
T181	0	58	0	0
T182	0	24	0	0
T183	0	49	0	0
T184	0	26	0	0
T185	0	23	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	3008	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	24	0	0
T76	0	34	0	0
T78	0	52	0	0
T92	11388	0	0	0
T127	29009	59	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	41	0	0
T180	0	21	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0
T190	0	37	0	0
T191	0	28	0	0
T192	0	51	0	0
T193	0	24	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2295	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	2	0	0
T76	0	16	0	0
T92	11388	0	0	0
T127	29009	34	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	35	0	0
T180	0	21	0	0
T181	0	54	0	0
T182	0	20	0	0
T183	0	45	0	0
T184	0	11	0	0
T185	0	27	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2568	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	16	0	0
T76	0	24	0	0
T92	11388	0	0	0
T127	29009	38	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	36	0	0
T180	0	44	0	0
T181	0	42	0	0
T182	0	27	0	0
T183	0	39	0	0
T184	0	23	0	0
T185	0	22	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2560	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	11	0	0
T76	0	31	0	0
T92	11388	0	0	0
T127	29009	32	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	25	0	0
T180	0	39	0	0
T181	0	54	0	0
T182	0	48	0	0
T183	0	33	0	0
T185	0	11	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0
T194	0	25	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2343	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	25	0	0
T76	0	29	0	0
T92	11388	0	0	0
T127	29009	43	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	26	0	0
T180	0	41	0	0
T181	0	45	0	0
T182	0	10	0	0
T183	0	56	0	0
T184	0	19	0	0
T185	0	31	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2529	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	12	0	0
T76	0	25	0	0
T92	11388	0	0	0
T127	29009	32	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	67	0	0
T180	0	42	0	0
T181	0	48	0	0
T182	0	29	0	0
T183	0	32	0	0
T184	0	13	0	0
T185	0	45	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2397	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	14	0	0
T76	0	20	0	0
T92	11388	0	0	0
T127	29009	23	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	28	0	0
T180	0	19	0	0
T181	0	57	0	0
T182	0	19	0	0
T183	0	28	0	0
T184	0	11	0	0
T185	0	24	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2732	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	11	0	0
T76	0	33	0	0
T92	11388	0	0	0
T127	29009	31	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	17	0	0
T180	0	50	0	0
T181	0	56	0	0
T182	0	23	0	0
T183	0	47	0	0
T184	0	24	0	0
T185	0	39	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2506	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	11	0	0
T76	0	33	0	0
T92	11388	0	0	0
T127	29009	34	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	32	0	0
T180	0	45	0	0
T181	0	49	0	0
T182	0	24	0	0
T183	0	30	0	0
T184	0	14	0	0
T185	0	37	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2418	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	38	0	0
T76	0	26	0	0
T92	11388	0	0	0
T127	29009	42	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	28	0	0
T180	0	35	0	0
T181	0	43	0	0
T182	0	19	0	0
T183	0	6	0	0
T184	0	14	0	0
T185	0	29	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2252	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	5	0	0
T76	0	31	0	0
T92	11388	0	0	0
T127	29009	16	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	26	0	0
T180	0	44	0	0
T181	0	57	0	0
T182	0	27	0	0
T183	0	30	0	0
T184	0	8	0	0
T185	0	16	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2534	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	3	0	0
T76	0	28	0	0
T92	11388	0	0	0
T127	29009	26	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	31	0	0
T180	0	39	0	0
T181	0	58	0	0
T182	0	24	0	0
T183	0	32	0	0
T184	0	8	0	0
T185	0	33	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2383	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	13	0	0
T76	0	32	0	0
T92	11388	0	0	0
T127	29009	30	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	22	0	0
T180	0	17	0	0
T181	0	59	0	0
T182	0	31	0	0
T183	0	41	0	0
T184	0	19	0	0
T185	0	30	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2473	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	21	0	0
T76	0	37	0	0
T92	11388	0	0	0
T127	29009	27	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	44	0	0
T180	0	24	0	0
T181	0	81	0	0
T182	0	33	0	0
T183	0	38	0	0
T184	0	16	0	0
T185	0	44	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2542	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	20	0	0
T76	0	11	0	0
T92	11388	0	0	0
T127	29009	24	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	23	0	0
T180	0	26	0	0
T181	0	39	0	0
T182	0	30	0	0
T183	0	16	0	0
T184	0	4	0	0
T185	0	32	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2261	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	7	0	0
T76	0	35	0	0
T92	11388	0	0	0
T127	29009	20	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	29	0	0
T180	0	17	0	0
T181	0	67	0	0
T182	0	3	0	0
T183	0	28	0	0
T184	0	17	0	0
T185	0	15	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2474	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	16	0	0
T76	0	43	0	0
T92	11388	0	0	0
T127	29009	30	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	20	0	0
T180	0	10	0	0
T181	0	51	0	0
T182	0	45	0	0
T183	0	39	0	0
T184	0	7	0	0
T185	0	28	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2475	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	16	0	0
T76	0	11	0	0
T92	11388	0	0	0
T127	29009	34	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	17	0	0
T180	0	57	0	0
T181	0	37	0	0
T182	0	35	0	0
T183	0	34	0	0
T184	0	12	0	0
T185	0	23	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2570	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T76	0	22	0	0
T92	11388	0	0	0
T127	29009	26	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	24	0	0
T180	0	36	0	0
T181	0	60	0	0
T182	0	13	0	0
T183	0	56	0	0
T184	0	17	0	0
T185	0	38	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0
T194	0	19	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2524	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	1	0	0
T76	0	21	0	0
T92	11388	0	0	0
T127	29009	31	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	26	0	0
T180	0	27	0	0
T181	0	53	0	0
T182	0	28	0	0
T183	0	24	0	0
T184	0	10	0	0
T185	0	50	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2471	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	11	0	0
T76	0	25	0	0
T92	11388	0	0	0
T127	29009	26	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	18	0	0
T180	0	18	0	0
T181	0	56	0	0
T182	0	35	0	0
T183	0	27	0	0
T184	0	47	0	0
T185	0	31	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2475	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	12	0	0
T76	0	19	0	0
T92	11388	0	0	0
T127	29009	20	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	31	0	0
T180	0	42	0	0
T181	0	40	0	0
T182	0	45	0	0
T183	0	55	0	0
T184	0	5	0	0
T185	0	21	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23183422	2455	0	0
T4	125271	0	0	0
T31	1932	0	0	0
T54	0	11	0	0
T76	0	23	0	0
T92	11388	0	0	0
T127	29009	20	0	0
T128	17465	0	0	0
T138	782617	0	0	0
T179	0	16	0	0
T180	0	35	0	0
T181	0	73	0	0
T182	0	22	0	0
T183	0	32	0	0
T184	0	21	0	0
T185	0	15	0	0
T186	5889	0	0	0
T187	9109	0	0	0
T188	5645	0	0	0
T189	11133	0	0	0