Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3431573	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

595690

1

T1

329

T2

141

T3

74

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3620131	1			T1	9938		T2	567		T3	93
values[0x0]	202538	1			T1	125		T2	31		T3	25
values[0x1]	204594	1			T1	130		T2	40		T3	25

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2345292	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1681971

1

T1

3606

T2

306

T3

98

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	78339	1			T1	50		T3	5		T11	41
valid_sources[0x01]	21127	1			T1	30		T11	37		T4	4
valid_sources[0x02]	14014	1			T1	34		T11	44		T4	35
valid_sources[0x03]	19912	1			T1	49		T3	7		T11	59
valid_sources[0x04]	12821	1			T1	26		T11	41		T4	11
valid_sources[0x05]	12661	1			T1	37		T11	46		T4	28
valid_sources[0x06]	12516	1			T1	35		T11	47		T4	2
valid_sources[0x07]	14850	1			T1	33		T11	35		T4	12
valid_sources[0x08]	13397	1			T1	45		T3	10		T11	57
valid_sources[0x09]	17212	1			T1	36		T11	34		T4	4
valid_sources[0x0a]	12683	1			T1	42		T11	46		T4	26
valid_sources[0x0b]	12675	1			T1	34		T11	43		T4	11
valid_sources[0x0c]	16936	1			T1	52		T3	1		T11	54
valid_sources[0x0d]	12951	1			T1	37		T11	53		T4	6
valid_sources[0x0e]	22249	1			T1	36		T11	66		T4	17
valid_sources[0x0f]	17444	1			T1	39		T3	1		T11	49
valid_sources[0x10]	12998	1			T1	31		T3	2		T11	44
valid_sources[0x11]	32446	1			T1	37		T11	39		T4	10
valid_sources[0x12]	16479	1			T1	40		T11	52		T4	6
valid_sources[0x13]	15970	1			T1	36		T3	5		T11	36
valid_sources[0x14]	20681	1			T1	42		T3	1		T11	40
valid_sources[0x15]	12708	1			T1	59		T11	57		T4	25
valid_sources[0x16]	12664	1			T1	37		T3	1		T11	44
valid_sources[0x17]	16222	1			T1	41		T11	50		T4	3
valid_sources[0x18]	31168	1			T1	45		T11	47		T4	21
valid_sources[0x19]	13720	1			T1	37		T11	48		T4	19
valid_sources[0x1a]	13662	1			T1	49		T11	33		T4	21
valid_sources[0x1b]	14335	1			T1	27		T11	62		T4	19
valid_sources[0x1c]	13333	1			T1	48		T11	47		T4	16
valid_sources[0x1d]	16516	1			T1	49		T3	1		T11	52
valid_sources[0x1e]	14352	1			T1	36		T11	40		T4	11
valid_sources[0x1f]	13650	1			T1	30		T11	29		T4	25
valid_sources[0x20]	19636	1			T1	36		T11	40		T4	18
valid_sources[0x21]	13656	1			T1	63		T3	1		T11	34
valid_sources[0x22]	13680	1			T1	35		T3	2		T11	36
valid_sources[0x23]	13209	1			T1	48		T3	2		T11	52
valid_sources[0x24]	16349	1			T1	49		T11	45		T4	13
valid_sources[0x25]	12526	1			T1	26		T11	43		T4	9
valid_sources[0x26]	18415	1			T1	39		T3	2		T11	53
valid_sources[0x27]	14492	1			T1	38		T11	39		T4	31
valid_sources[0x28]	21551	1			T1	39		T11	41		T4	21
valid_sources[0x29]	13065	1			T1	41		T11	55		T4	12
valid_sources[0x2a]	12466	1			T1	50		T11	41		T4	35
valid_sources[0x2b]	12685	1			T1	60		T11	61		T4	9
valid_sources[0x2c]	12439	1			T1	30		T11	42		T4	22
valid_sources[0x2d]	13801	1			T1	35		T11	34		T4	18
valid_sources[0x2e]	15657	1			T1	53		T3	5		T11	41
valid_sources[0x2f]	50891	1			T1	46		T11	51		T4	16
valid_sources[0x30]	12795	1			T1	34		T11	72		T4	8
valid_sources[0x31]	13196	1			T1	31		T11	42		T4	18
valid_sources[0x32]	12910	1			T1	22		T11	40		T4	6
valid_sources[0x33]	13372	1			T1	35		T11	40		T4	10
valid_sources[0x34]	13182	1			T1	56		T11	33		T4	21
valid_sources[0x35]	14357	1			T1	33		T11	51		T4	7
valid_sources[0x36]	13932	1			T1	36		T11	49		T4	27
valid_sources[0x37]	12540	1			T1	41		T3	1		T11	47
valid_sources[0x38]	16890	1			T1	39		T11	40		T4	2
valid_sources[0x39]	13287	1			T1	34		T11	49		T4	10
valid_sources[0x3a]	20303	1			T1	41		T11	17		T4	21
valid_sources[0x3b]	14303	1			T1	47		T11	47		T4	18
valid_sources[0x3c]	13195	1			T1	43		T2	638		T11	40
valid_sources[0x3d]	13044	1			T1	28		T11	37		T4	8
valid_sources[0x3e]	21929	1			T1	33		T11	46		T4	18
valid_sources[0x3f]	22755	1			T1	40		T11	45		T4	1
valid_sources[0x40]	18347	1			T1	28		T11	50		T4	19
valid_sources[0x41]	22334	1			T1	36		T11	49		T4	13
valid_sources[0x42]	13072	1			T1	48		T11	30		T4	30
valid_sources[0x43]	13300	1			T1	36		T11	45		T4	4
valid_sources[0x44]	13639	1			T1	56		T3	4		T11	52
valid_sources[0x45]	14003	1			T1	38		T11	35		T4	34
valid_sources[0x46]	13728	1			T1	46		T11	62		T4	50
valid_sources[0x47]	13632	1			T1	48		T11	53		T4	11
valid_sources[0x48]	14436	1			T1	41		T3	1		T11	51
valid_sources[0x49]	12577	1			T1	38		T11	45		T4	16
valid_sources[0x4a]	14871	1			T1	36		T11	52		T4	3
valid_sources[0x4b]	12497	1			T1	51		T11	44		T4	19
valid_sources[0x4c]	14110	1			T1	48		T11	43		T4	21
valid_sources[0x4d]	22806	1			T1	40		T11	30		T4	16
valid_sources[0x4e]	12512	1			T1	37		T11	39		T4	11
valid_sources[0x4f]	13409	1			T1	30		T11	31		T4	8
valid_sources[0x50]	15916	1			T1	32		T11	56		T4	1
valid_sources[0x51]	13968	1			T1	28		T11	44		T4	10
valid_sources[0x52]	13596	1			T1	34		T11	32		T4	11
valid_sources[0x53]	14932	1			T1	46		T11	50		T4	11
valid_sources[0x54]	12452	1			T1	55		T11	35		T4	10
valid_sources[0x55]	12040	1			T1	34		T11	55		T4	14
valid_sources[0x56]	16737	1			T1	50		T11	34		T4	19
valid_sources[0x57]	13722	1			T1	49		T11	44		T4	1
valid_sources[0x58]	14729	1			T1	40		T11	41		T4	8
valid_sources[0x59]	19329	1			T1	40		T11	40		T4	5
valid_sources[0x5a]	37743	1			T1	55		T11	53		T4	12
valid_sources[0x5b]	12588	1			T1	46		T3	3		T11	52
valid_sources[0x5c]	12690	1			T1	41		T11	55		T4	12
valid_sources[0x5d]	12367	1			T1	37		T11	49		T4	3
valid_sources[0x5e]	13095	1			T1	31		T11	51		T4	9
valid_sources[0x5f]	15211	1			T1	41		T3	4		T11	47
valid_sources[0x60]	15733	1			T1	39		T11	43		T4	3
valid_sources[0x61]	15316	1			T1	34		T11	47		T4	23
valid_sources[0x62]	12655	1			T1	39		T3	2		T11	31
valid_sources[0x63]	12373	1			T1	36		T11	50		T4	9
valid_sources[0x64]	12972	1			T1	41		T11	34		T12	2
valid_sources[0x65]	12743	1			T1	36		T11	47		T4	9
valid_sources[0x66]	12775	1			T1	52		T11	39		T4	11
valid_sources[0x67]	12561	1			T1	29		T11	40		T4	19
valid_sources[0x68]	14983	1			T1	29		T11	44		T4	18
valid_sources[0x69]	13187	1			T1	41		T3	5		T11	46
valid_sources[0x6a]	16193	1			T1	44		T11	45		T4	2
valid_sources[0x6b]	15234	1			T1	36		T11	42		T4	23
valid_sources[0x6c]	12344	1			T1	38		T11	47		T4	14
valid_sources[0x6d]	14425	1			T1	33		T11	37		T4	12
valid_sources[0x6e]	13763	1			T1	40		T11	44		T4	6
valid_sources[0x6f]	18403	1			T1	41		T3	1		T11	33
valid_sources[0x70]	12585	1			T1	38		T11	45		T4	20
valid_sources[0x71]	12686	1			T1	39		T11	44		T4	12
valid_sources[0x72]	19009	1			T1	30		T11	47		T4	13
valid_sources[0x73]	17414	1			T1	45		T11	35		T4	27
valid_sources[0x74]	13106	1			T1	38		T3	9		T11	37
valid_sources[0x75]	12803	1			T1	45		T11	37		T4	29
valid_sources[0x76]	13640	1			T1	36		T11	44		T4	21
valid_sources[0x77]	13287	1			T1	31		T11	34		T4	36
valid_sources[0x78]	19574	1			T1	28		T11	55		T4	22
valid_sources[0x79]	13962	1			T1	42		T11	45		T4	17
valid_sources[0x7a]	13745	1			T1	34		T11	32		T4	14
valid_sources[0x7b]	14244	1			T1	47		T11	58		T4	37
valid_sources[0x7c]	13443	1			T1	43		T11	46		T4	10
valid_sources[0x7d]	12865	1			T1	44		T11	37		T4	15
valid_sources[0x7e]	16129	1			T1	40		T11	54		T4	19
valid_sources[0x7f]	13644	1			T1	47		T11	45		T4	4
valid_sources[0x80]	12907	1			T1	38		T3	2		T11	52

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

319032

1

T1

180

T2

123

T3

37

values[0x0]

all_enables

biggest_size

145521

1

T1

82

T2

12

T3

19

values[0x1]

all_enables

biggest_size

131137

1

T1

67

T2

6

T3

18