Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
20555282 |
20390221 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20555282 |
20390221 |
0 |
0 |
T1 |
35130 |
35037 |
0 |
0 |
T2 |
5357 |
5225 |
0 |
0 |
T3 |
1529 |
1475 |
0 |
0 |
T4 |
20786 |
20523 |
0 |
0 |
T11 |
156414 |
156321 |
0 |
0 |
T12 |
36649 |
36559 |
0 |
0 |
T13 |
4746 |
4683 |
0 |
0 |
T14 |
6273 |
6222 |
0 |
0 |
T15 |
6937 |
6757 |
0 |
0 |
T16 |
7021 |
6966 |
0 |
0 |