Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2990049	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

615243

1

T1

3058

T2

5090

T3

146

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3186086	1			T1	12778		T2	7347		T3	1276
values[0x0]	207728	1			T1	93		T2	1811		T3	48
values[0x1]	211478	1			T1	89		T2	1859		T3	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2052865	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1552427

1

T1

5913

T2

6479

T3

533

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23248	1			T1	39		T4	3		T11	5
valid_sources[0x01]	10710	1			T1	40		T4	4		T11	5
valid_sources[0x02]	22802	1			T1	45		T4	4		T11	6
valid_sources[0x03]	12242	1			T1	35		T4	1		T11	4
valid_sources[0x04]	13225	1			T1	24		T4	2		T11	14
valid_sources[0x05]	11107	1			T1	15		T4	3		T11	5
valid_sources[0x06]	13117	1			T1	36		T4	3		T11	5
valid_sources[0x07]	11104	1			T1	28		T4	5		T11	14
valid_sources[0x08]	11669	1			T1	21		T11	4		T12	10
valid_sources[0x09]	11829	1			T1	22		T4	1		T11	2
valid_sources[0x0a]	11967	1			T1	21		T4	1		T11	1
valid_sources[0x0b]	11748	1			T1	24		T4	4		T11	13
valid_sources[0x0c]	12431	1			T1	40		T4	5		T11	3
valid_sources[0x0d]	15346	1			T1	49		T4	1		T11	3
valid_sources[0x0e]	11433	1			T1	33		T4	2		T11	8
valid_sources[0x0f]	12757	1			T1	44		T4	5		T11	5
valid_sources[0x10]	11715	1			T1	37		T4	1		T11	10
valid_sources[0x11]	11758	1			T1	28		T4	1		T11	9
valid_sources[0x12]	11012	1			T1	30		T4	1		T11	10
valid_sources[0x13]	11706	1			T1	29		T4	2		T11	2
valid_sources[0x14]	11120	1			T1	35		T4	4		T11	3
valid_sources[0x15]	12057	1			T1	22		T4	3		T11	15
valid_sources[0x16]	11717	1			T1	25		T4	4		T11	7
valid_sources[0x17]	21238	1			T1	30		T2	5390		T4	2
valid_sources[0x18]	11777	1			T1	34		T4	1		T11	6
valid_sources[0x19]	12483	1			T1	34		T4	3		T11	7
valid_sources[0x1a]	11220	1			T1	48		T11	13		T12	6
valid_sources[0x1b]	12294	1			T1	14		T4	1		T11	8
valid_sources[0x1c]	14067	1			T1	32		T4	4		T11	3
valid_sources[0x1d]	11154	1			T1	30		T11	10		T12	8
valid_sources[0x1e]	11183	1			T1	50		T4	5		T11	2
valid_sources[0x1f]	71236	1			T1	24		T4	3		T11	1
valid_sources[0x20]	56431	1			T1	56		T4	1		T11	11
valid_sources[0x21]	11509	1			T1	36		T11	3		T12	8
valid_sources[0x22]	11170	1			T1	42		T4	2		T11	1
valid_sources[0x23]	11037	1			T1	18		T4	2		T11	2
valid_sources[0x24]	10854	1			T1	46		T4	6		T11	4
valid_sources[0x25]	10536	1			T1	16		T4	1		T11	2
valid_sources[0x26]	11267	1			T1	23		T4	2		T11	5
valid_sources[0x27]	11380	1			T1	36		T4	3		T11	3
valid_sources[0x28]	11631	1			T1	41		T4	4		T11	11
valid_sources[0x29]	17028	1			T1	22		T4	6		T11	3
valid_sources[0x2a]	24825	1			T1	37		T4	5		T11	5
valid_sources[0x2b]	15842	1			T1	17		T11	7		T12	6
valid_sources[0x2c]	11201	1			T1	47		T11	6		T12	7
valid_sources[0x2d]	11345	1			T1	29		T4	4		T11	6
valid_sources[0x2e]	11307	1			T1	27		T4	2		T11	16
valid_sources[0x2f]	12625	1			T1	112		T4	5		T11	7
valid_sources[0x30]	11516	1			T1	27		T4	2		T11	7
valid_sources[0x31]	14326	1			T1	33		T4	2		T11	9
valid_sources[0x32]	11636	1			T1	26		T11	8		T12	7
valid_sources[0x33]	27551	1			T1	30		T4	2		T11	8
valid_sources[0x34]	15478	1			T1	41		T4	3		T11	7
valid_sources[0x35]	12040	1			T1	29		T4	1		T11	5
valid_sources[0x36]	14125	1			T1	20		T4	1		T11	7
valid_sources[0x37]	11090	1			T1	32		T4	5		T11	5
valid_sources[0x38]	10848	1			T1	20		T4	4		T11	5
valid_sources[0x39]	11817	1			T1	34		T4	5		T11	13
valid_sources[0x3a]	12180	1			T1	48		T4	6		T11	17
valid_sources[0x3b]	12046	1			T1	41		T4	3		T11	12
valid_sources[0x3c]	11372	1			T1	44		T4	2		T11	4
valid_sources[0x3d]	11237	1			T1	39		T4	8		T11	8
valid_sources[0x3e]	10921	1			T1	32		T4	2		T11	4
valid_sources[0x3f]	11709	1			T1	27		T4	2		T11	3
valid_sources[0x40]	11783	1			T1	23		T4	2		T11	2
valid_sources[0x41]	11274	1			T1	39		T4	2		T11	3
valid_sources[0x42]	13877	1			T1	35		T4	6		T11	7
valid_sources[0x43]	11010	1			T1	33		T4	1		T11	7
valid_sources[0x44]	12139	1			T1	16		T4	2		T11	1
valid_sources[0x45]	11356	1			T1	31		T4	5		T11	5
valid_sources[0x46]	12018	1			T1	27		T3	1364		T4	4
valid_sources[0x47]	14207	1			T1	44		T4	2		T11	7
valid_sources[0x48]	11864	1			T1	42		T4	2		T11	4
valid_sources[0x49]	10660	1			T1	28		T4	1		T11	4
valid_sources[0x4a]	11514	1			T1	56		T4	1		T11	4
valid_sources[0x4b]	13774	1			T1	28		T4	5		T11	5
valid_sources[0x4c]	12006	1			T1	30		T4	1		T11	2
valid_sources[0x4d]	12872	1			T1	37		T4	2		T11	4
valid_sources[0x4e]	11234	1			T1	43		T4	4		T11	5
valid_sources[0x4f]	12511	1			T1	25		T4	5		T12	4
valid_sources[0x50]	22900	1			T1	22		T4	4		T11	4
valid_sources[0x51]	11071	1			T1	34		T4	2		T11	15
valid_sources[0x52]	11724	1			T1	36		T4	1		T11	5
valid_sources[0x53]	12117	1			T1	29		T4	5		T11	2
valid_sources[0x54]	49385	1			T1	29		T4	4		T11	3
valid_sources[0x55]	11009	1			T1	36		T12	8		T13	5
valid_sources[0x56]	11077	1			T1	23		T4	1		T11	9
valid_sources[0x57]	12978	1			T1	17		T4	5		T11	2
valid_sources[0x58]	12854	1			T1	29		T4	2		T11	8
valid_sources[0x59]	13065	1			T1	27		T4	2		T11	4
valid_sources[0x5a]	12149	1			T1	46		T4	2		T11	2
valid_sources[0x5b]	10995	1			T1	38		T4	3		T11	7
valid_sources[0x5c]	11783	1			T1	26		T11	5		T12	9
valid_sources[0x5d]	16110	1			T1	29		T4	1		T11	2
valid_sources[0x5e]	10873	1			T1	31		T4	2		T11	6
valid_sources[0x5f]	11016	1			T1	34		T4	1		T11	4
valid_sources[0x60]	11774	1			T1	50		T4	5		T11	7
valid_sources[0x61]	11550	1			T1	24		T4	3		T11	7
valid_sources[0x62]	12080	1			T1	21		T4	1		T11	11
valid_sources[0x63]	11009	1			T1	46		T4	1		T11	10
valid_sources[0x64]	11579	1			T1	48		T4	1		T11	2
valid_sources[0x65]	10896	1			T1	35		T4	2		T11	6
valid_sources[0x66]	14304	1			T1	53		T4	2		T11	8
valid_sources[0x67]	11213	1			T1	33		T4	1		T11	5
valid_sources[0x68]	13233	1			T1	41		T4	2		T11	6
valid_sources[0x69]	11177	1			T1	31		T4	3		T11	5
valid_sources[0x6a]	11438	1			T1	34		T4	2		T11	7
valid_sources[0x6b]	20624	1			T1	25		T4	3		T11	16
valid_sources[0x6c]	10610	1			T1	40		T4	1		T11	2
valid_sources[0x6d]	11279	1			T1	28		T4	3		T11	8
valid_sources[0x6e]	13367	1			T1	24		T4	4		T11	3
valid_sources[0x6f]	10868	1			T1	32		T4	2		T11	2
valid_sources[0x70]	12678	1			T1	58		T4	3		T11	11
valid_sources[0x71]	11400	1			T1	36		T4	3		T11	8
valid_sources[0x72]	11061	1			T1	38		T4	3		T11	4
valid_sources[0x73]	25720	1			T1	39		T4	3		T11	4
valid_sources[0x74]	11489	1			T1	36		T4	3		T11	6
valid_sources[0x75]	65916	1			T1	32		T4	7		T11	3
valid_sources[0x76]	11448	1			T1	30		T11	4		T12	7
valid_sources[0x77]	14454	1			T1	36		T4	1		T11	2
valid_sources[0x78]	63769	1			T1	29		T4	3		T11	6
valid_sources[0x79]	10754	1			T1	34		T4	4		T11	10
valid_sources[0x7a]	11451	1			T1	38		T4	5		T11	3
valid_sources[0x7b]	10797	1			T1	52		T4	1		T11	4
valid_sources[0x7c]	12561	1			T1	106		T4	1		T11	3
valid_sources[0x7d]	18141	1			T1	67		T4	1		T11	5
valid_sources[0x7e]	11630	1			T1	28		T4	2		T11	10
valid_sources[0x7f]	18791	1			T1	39		T4	2		T11	5
valid_sources[0x80]	11021	1			T1	14		T4	1		T11	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

331085

1

T1

2931

T2

2711

T3

119

values[0x0]

all_enables

biggest_size

149251

1

T1

69

T2

1260

T3

21

values[0x1]

all_enables

biggest_size

134907

1

T1

58

T2

1119

T3

6