Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
21179842 |
21017954 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21179842 |
21017954 |
0 |
0 |
T1 |
38035 |
37864 |
0 |
0 |
T2 |
137621 |
136067 |
0 |
0 |
T3 |
5427 |
5356 |
0 |
0 |
T4 |
2218 |
2137 |
0 |
0 |
T11 |
5571 |
5494 |
0 |
0 |
T12 |
5871 |
5777 |
0 |
0 |
T13 |
7146 |
7087 |
0 |
0 |
T14 |
4133 |
4060 |
0 |
0 |
T15 |
1772 |
1714 |
0 |
0 |
T16 |
7140 |
7055 |
0 |
0 |