Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23030086	17907	0	0
attest_sw_binding_0_rd_A	23030086	4125	0	0
attest_sw_binding_1_rd_A	23030086	4196	0	0
attest_sw_binding_2_rd_A	23030086	3869	0	0
attest_sw_binding_3_rd_A	23030086	4027	0	0
attest_sw_binding_4_rd_A	23030086	3949	0	0
attest_sw_binding_5_rd_A	23030086	4127	0	0
attest_sw_binding_6_rd_A	23030086	3762	0	0
attest_sw_binding_7_rd_A	23030086	3921	0	0
intr_enable_rd_A	23030086	4641	0	0
key_version_rd_A	23030086	3775	0	0
max_creator_key_ver_regwen_rd_A	23030086	4072	0	0
max_owner_int_key_ver_regwen_rd_A	23030086	3752	0	0
max_owner_key_ver_regwen_rd_A	23030086	3999	0	0
reseed_interval_regwen_rd_A	23030086	3900	0	0
salt_0_rd_A	23030086	3903	0	0
salt_1_rd_A	23030086	4051	0	0
salt_2_rd_A	23030086	3875	0	0
salt_3_rd_A	23030086	4010	0	0
salt_4_rd_A	23030086	4089	0	0
salt_5_rd_A	23030086	3902	0	0
salt_6_rd_A	23030086	3824	0	0
salt_7_rd_A	23030086	4060	0	0
sealing_sw_binding_0_rd_A	23030086	3958	0	0
sealing_sw_binding_1_rd_A	23030086	3867	0	0
sealing_sw_binding_2_rd_A	23030086	3961	0	0
sealing_sw_binding_3_rd_A	23030086	3946	0	0
sealing_sw_binding_4_rd_A	23030086	3967	0	0
sealing_sw_binding_5_rd_A	23030086	3890	0	0
sealing_sw_binding_6_rd_A	23030086	3932	0	0
sealing_sw_binding_7_rd_A	23030086	3993	0	0
sideload_clear_rd_A	23030086	4083	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	17907	0	0
T24	6870	0	0	0
T36	4638	0	0	0
T52	9608	154	0	0
T57	16613	496	0	0
T106	1006	0	0	0
T109	7811	0	0	0
T110	25656	0	0	0
T111	0	240	0	0
T123	0	680	0	0
T124	0	333	0	0
T125	0	1896	0	0
T127	0	220	0	0
T128	0	45	0	0
T129	0	1390	0	0
T130	28356	0	0	0
T131	3175	0	0	0
T132	10029	0	0	0
T134	0	551	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	4125	0	0
T34	5853	0	0	0
T114	0	115	0	0
T117	0	41	0	0
T143	0	3	0	0
T146	0	233	0	0
T151	0	66	0	0
T158	0	89	0	0
T167	0	34	0	0
T174	21984	15	0	0
T175	0	14	0	0
T176	0	16	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	4196	0	0
T34	5853	0	0	0
T114	0	119	0	0
T117	0	17	0	0
T143	0	2	0	0
T146	0	239	0	0
T151	0	85	0	0
T158	0	75	0	0
T167	0	37	0	0
T174	21984	18	0	0
T176	0	14	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0
T185	0	3	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3869	0	0
T34	5853	0	0	0
T114	0	106	0	0
T117	0	31	0	0
T143	0	4	0	0
T146	0	259	0	0
T151	0	74	0	0
T158	0	79	0	0
T167	0	39	0	0
T174	21984	37	0	0
T175	0	6	0	0
T176	0	11	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	4027	0	0
T34	5853	0	0	0
T114	0	115	0	0
T117	0	23	0	0
T143	0	3	0	0
T146	0	229	0	0
T151	0	91	0	0
T158	0	90	0	0
T167	0	45	0	0
T174	21984	30	0	0
T175	0	3	0	0
T176	0	6	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3949	0	0
T34	5853	0	0	0
T114	0	94	0	0
T117	0	12	0	0
T143	0	2	0	0
T146	0	256	0	0
T151	0	67	0	0
T158	0	79	0	0
T167	0	37	0	0
T174	21984	22	0	0
T175	0	8	0	0
T176	0	3	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	4127	0	0
T34	5853	0	0	0
T114	0	99	0	0
T117	0	18	0	0
T143	0	2	0	0
T146	0	289	0	0
T151	0	63	0	0
T158	0	83	0	0
T167	0	37	0	0
T174	21984	20	0	0
T175	0	6	0	0
T176	0	3	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3762	0	0
T34	5853	0	0	0
T114	0	126	0	0
T117	0	28	0	0
T143	0	5	0	0
T146	0	228	0	0
T151	0	73	0	0
T158	0	76	0	0
T167	0	60	0	0
T174	21984	24	0	0
T175	0	8	0	0
T176	0	6	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3921	0	0
T34	5853	0	0	0
T114	0	117	0	0
T117	0	22	0	0
T143	0	1	0	0
T146	0	274	0	0
T151	0	88	0	0
T158	0	85	0	0
T167	0	57	0	0
T174	21984	29	0	0
T175	0	12	0	0
T176	0	2	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	4641	0	0
T2	137621	54	0	0
T3	5427	0	0	0
T4	2218	0	0	0
T11	5571	0	0	0
T12	5871	0	0	0
T13	7146	0	0	0
T14	4133	0	0	0
T15	1772	0	0	0
T16	7140	0	0	0
T23	0	9	0	0
T35	6777	0	0	0
T73	0	32	0	0
T174	0	80	0	0
T186	0	78	0	0
T187	0	24	0	0
T188	0	53	0	0
T189	0	12	0	0
T190	0	36	0	0
T191	0	24	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3775	0	0
T34	5853	0	0	0
T114	0	116	0	0
T117	0	28	0	0
T143	0	9	0	0
T144	0	2	0	0
T146	0	265	0	0
T151	0	83	0	0
T158	0	65	0	0
T167	0	36	0	0
T174	21984	38	0	0
T176	0	5	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	4072	0	0
T34	5853	0	0	0
T114	0	115	0	0
T117	0	36	0	0
T143	0	1	0	0
T144	0	7	0	0
T146	0	235	0	0
T151	0	73	0	0
T158	0	64	0	0
T167	0	48	0	0
T174	21984	23	0	0
T176	0	9	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3752	0	0
T34	5853	0	0	0
T114	0	103	0	0
T117	0	20	0	0
T143	0	7	0	0
T144	0	4	0	0
T146	0	260	0	0
T151	0	96	0	0
T158	0	88	0	0
T167	0	42	0	0
T174	21984	33	0	0
T176	0	4	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3999	0	0
T34	5853	0	0	0
T114	0	107	0	0
T117	0	14	0	0
T143	0	5	0	0
T146	0	261	0	0
T151	0	82	0	0
T158	0	73	0	0
T167	0	50	0	0
T174	21984	26	0	0
T175	0	7	0	0
T176	0	7	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3900	0	0
T34	5853	0	0	0
T114	0	104	0	0
T117	0	13	0	0
T143	0	2	0	0
T146	0	244	0	0
T151	0	81	0	0
T158	0	82	0	0
T167	0	27	0	0
T174	21984	34	0	0
T175	0	2	0	0
T176	0	7	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3903	0	0
T34	5853	0	0	0
T114	0	111	0	0
T117	0	33	0	0
T143	0	4	0	0
T146	0	265	0	0
T151	0	43	0	0
T158	0	78	0	0
T167	0	42	0	0
T174	21984	14	0	0
T175	0	12	0	0
T176	0	11	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	4051	0	0
T34	5853	0	0	0
T114	0	104	0	0
T117	0	9	0	0
T143	0	5	0	0
T146	0	293	0	0
T151	0	103	0	0
T158	0	84	0	0
T167	0	56	0	0
T174	21984	21	0	0
T175	0	34	0	0
T176	0	13	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3875	0	0
T34	5853	0	0	0
T114	0	102	0	0
T117	0	11	0	0
T143	0	5	0	0
T146	0	225	0	0
T151	0	82	0	0
T158	0	71	0	0
T167	0	38	0	0
T174	21984	30	0	0
T175	0	4	0	0
T176	0	6	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	4010	0	0
T34	5853	0	0	0
T114	0	115	0	0
T117	0	15	0	0
T143	0	5	0	0
T146	0	284	0	0
T151	0	89	0	0
T158	0	77	0	0
T167	0	38	0	0
T174	21984	27	0	0
T175	0	3	0	0
T176	0	7	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	4089	0	0
T34	5853	0	0	0
T114	0	99	0	0
T117	0	30	0	0
T143	0	1	0	0
T146	0	285	0	0
T151	0	81	0	0
T158	0	90	0	0
T167	0	60	0	0
T174	21984	35	0	0
T175	0	18	0	0
T176	0	9	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3902	0	0
T34	5853	0	0	0
T114	0	106	0	0
T117	0	15	0	0
T143	0	2	0	0
T144	0	2	0	0
T146	0	310	0	0
T151	0	74	0	0
T158	0	76	0	0
T167	0	54	0	0
T174	21984	24	0	0
T176	0	4	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3824	0	0
T34	5853	0	0	0
T114	0	109	0	0
T117	0	25	0	0
T143	0	4	0	0
T144	0	1	0	0
T146	0	225	0	0
T151	0	63	0	0
T158	0	99	0	0
T167	0	47	0	0
T174	21984	19	0	0
T176	0	7	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	4060	0	0
T34	5853	0	0	0
T114	0	109	0	0
T117	0	17	0	0
T143	0	1	0	0
T146	0	269	0	0
T151	0	78	0	0
T158	0	79	0	0
T167	0	53	0	0
T174	21984	38	0	0
T175	0	21	0	0
T176	0	7	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3958	0	0
T34	5853	0	0	0
T114	0	105	0	0
T117	0	29	0	0
T143	0	1	0	0
T146	0	244	0	0
T151	0	87	0	0
T158	0	67	0	0
T167	0	29	0	0
T174	21984	33	0	0
T175	0	13	0	0
T176	0	7	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3867	0	0
T34	5853	0	0	0
T114	0	110	0	0
T117	0	9	0	0
T144	0	4	0	0
T146	0	271	0	0
T151	0	87	0	0
T158	0	68	0	0
T167	0	31	0	0
T174	21984	52	0	0
T175	0	1	0	0
T176	0	4	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3961	0	0
T34	5853	0	0	0
T114	0	127	0	0
T117	0	13	0	0
T143	0	8	0	0
T146	0	277	0	0
T151	0	78	0	0
T158	0	67	0	0
T167	0	51	0	0
T174	21984	45	0	0
T175	0	11	0	0
T176	0	9	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3946	0	0
T34	5853	0	0	0
T114	0	94	0	0
T117	0	23	0	0
T144	0	7	0	0
T146	0	225	0	0
T151	0	90	0	0
T158	0	84	0	0
T167	0	39	0	0
T174	21984	22	0	0
T175	0	8	0	0
T176	0	13	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3967	0	0
T34	5853	0	0	0
T114	0	110	0	0
T117	0	20	0	0
T146	0	235	0	0
T151	0	87	0	0
T158	0	66	0	0
T167	0	43	0	0
T174	21984	22	0	0
T175	0	10	0	0
T176	0	9	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0
T185	0	8	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3890	0	0
T80	78750	0	0	0
T103	16822	0	0	0
T114	0	137	0	0
T117	0	29	0	0
T146	0	251	0	0
T151	0	73	0	0
T158	0	77	0	0
T167	0	47	0	0
T174	0	17	0	0
T175	0	17	0	0
T176	0	10	0	0
T192	4253	3	0	0
T193	4848	0	0	0
T194	7451	0	0	0
T195	3193	0	0	0
T196	52809	0	0	0
T197	124509	0	0	0
T198	18089	0	0	0
T199	12674	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3932	0	0
T34	5853	0	0	0
T114	0	107	0	0
T117	0	32	0	0
T119	0	57	0	0
T146	0	250	0	0
T151	0	74	0	0
T158	0	83	0	0
T167	0	37	0	0
T174	21984	45	0	0
T176	0	3	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0
T200	0	20	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	3993	0	0
T114	0	142	0	0
T117	0	14	0	0
T146	0	217	0	0
T151	0	73	0	0
T158	0	73	0	0
T167	0	56	0	0
T174	0	32	0	0
T175	0	8	0	0
T176	0	11	0	0
T201	8251	3	0	0
T202	30262	0	0	0
T203	2390	0	0	0
T204	2010	0	0	0
T205	15296	0	0	0
T206	4885	0	0	0
T207	7619	0	0	0
T208	5104	0	0	0
T209	8155	0	0	0
T210	7855	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030086	4083	0	0
T34	5853	0	0	0
T114	0	106	0	0
T117	0	28	0	0
T143	0	6	0	0
T146	0	293	0	0
T151	0	71	0	0
T158	0	79	0	0
T167	0	28	0	0
T174	21984	30	0	0
T175	0	7	0	0
T176	0	9	0	0
T177	6613	0	0	0
T178	1336	0	0	0
T179	5407	0	0	0
T180	14857	0	0	0
T181	3112	0	0	0
T182	31090	0	0	0
T183	18809	0	0	0
T184	44280	0	0	0