Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3117437	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

621320

1

T1

130

T2

274

T3

338

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3323744	1			T1	41383		T2	13852		T3	351
values[0x0]	205791	1			T1	38		T2	137		T3	144
values[0x1]	209222	1			T1	43		T2	142		T3	161

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2136691	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1602066

1

T1

13997

T2

4794

T3

416

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17414	1			T1	152		T2	65		T3	4
valid_sources[0x01]	11850	1			T1	191		T2	63		T3	1
valid_sources[0x02]	12030	1			T1	141		T2	40		T3	1
valid_sources[0x03]	11424	1			T1	173		T2	58		T3	2
valid_sources[0x04]	13789	1			T1	148		T2	37		T3	4
valid_sources[0x05]	14924	1			T1	187		T2	59		T4	4
valid_sources[0x06]	12441	1			T1	172		T2	63		T3	3
valid_sources[0x07]	13401	1			T1	158		T2	57		T3	7
valid_sources[0x08]	13694	1			T1	159		T2	48		T3	2
valid_sources[0x09]	11935	1			T1	167		T2	55		T3	4
valid_sources[0x0a]	11647	1			T1	142		T2	74		T6	1
valid_sources[0x0b]	15249	1			T1	161		T2	48		T3	5
valid_sources[0x0c]	12894	1			T1	164		T2	70		T3	4
valid_sources[0x0d]	12686	1			T1	172		T2	43		T3	3
valid_sources[0x0e]	20505	1			T1	161		T2	47		T3	3
valid_sources[0x0f]	12533	1			T1	154		T2	72		T4	3
valid_sources[0x10]	11409	1			T1	138		T2	63		T3	1
valid_sources[0x11]	13164	1			T1	164		T2	52		T3	9
valid_sources[0x12]	14014	1			T1	149		T2	76		T3	6
valid_sources[0x13]	22103	1			T1	158		T2	33		T4	3
valid_sources[0x14]	11189	1			T1	143		T2	47		T3	2
valid_sources[0x15]	44244	1			T1	184		T2	74		T3	2
valid_sources[0x16]	11464	1			T1	174		T2	52		T3	2
valid_sources[0x17]	11469	1			T1	141		T2	63		T3	6
valid_sources[0x18]	25747	1			T1	140		T2	55		T3	2
valid_sources[0x19]	13884	1			T1	173		T2	38		T3	5
valid_sources[0x1a]	12278	1			T1	159		T2	52		T6	1
valid_sources[0x1b]	12362	1			T1	150		T2	33		T3	2
valid_sources[0x1c]	12218	1			T1	171		T2	32		T4	3
valid_sources[0x1d]	13497	1			T1	150		T2	50		T4	3
valid_sources[0x1e]	13460	1			T1	165		T2	57		T3	3
valid_sources[0x1f]	11623	1			T1	155		T2	43		T3	4
valid_sources[0x20]	11973	1			T1	148		T2	51		T3	4
valid_sources[0x21]	12182	1			T1	160		T2	35		T3	2
valid_sources[0x22]	11018	1			T1	136		T2	47		T3	3
valid_sources[0x23]	12123	1			T1	177		T2	62		T6	4
valid_sources[0x24]	11160	1			T1	155		T2	43		T3	6
valid_sources[0x25]	12339	1			T1	169		T2	44		T3	2
valid_sources[0x26]	11881	1			T1	151		T2	50		T3	3
valid_sources[0x27]	13964	1			T1	160		T2	74		T6	1
valid_sources[0x28]	11848	1			T1	155		T2	41		T3	1
valid_sources[0x29]	37028	1			T1	166		T2	51		T3	6
valid_sources[0x2a]	11489	1			T1	146		T2	59		T3	5
valid_sources[0x2b]	11937	1			T1	170		T2	72		T3	8
valid_sources[0x2c]	27720	1			T1	155		T2	77		T4	5
valid_sources[0x2d]	11973	1			T1	176		T2	58		T4	1
valid_sources[0x2e]	11936	1			T1	195		T2	60		T3	1
valid_sources[0x2f]	14036	1			T1	180		T2	47		T3	5
valid_sources[0x30]	13472	1			T1	178		T2	59		T3	3
valid_sources[0x31]	22419	1			T1	185		T2	62		T3	8
valid_sources[0x32]	11321	1			T1	183		T2	52		T3	5
valid_sources[0x33]	11691	1			T1	147		T2	57		T6	4
valid_sources[0x34]	11306	1			T1	154		T2	62		T3	6
valid_sources[0x35]	12797	1			T1	169		T2	59		T3	3
valid_sources[0x36]	16300	1			T1	163		T2	54		T3	1
valid_sources[0x37]	12518	1			T1	148		T2	51		T3	5
valid_sources[0x38]	12612	1			T1	171		T2	52		T3	2
valid_sources[0x39]	12659	1			T1	154		T2	61		T3	6
valid_sources[0x3a]	12648	1			T1	156		T2	46		T3	3
valid_sources[0x3b]	48467	1			T1	188		T2	50		T3	1
valid_sources[0x3c]	12445	1			T1	156		T2	56		T3	1
valid_sources[0x3d]	19424	1			T1	146		T2	70		T3	2
valid_sources[0x3e]	12958	1			T1	142		T2	44		T3	1
valid_sources[0x3f]	13364	1			T1	164		T2	57		T3	5
valid_sources[0x40]	13939	1			T1	157		T2	72		T3	3
valid_sources[0x41]	12164	1			T1	178		T2	77		T4	3
valid_sources[0x42]	11823	1			T1	144		T2	57		T3	1
valid_sources[0x43]	14627	1			T1	154		T2	62		T6	3
valid_sources[0x44]	11317	1			T1	168		T2	51		T4	3
valid_sources[0x45]	11631	1			T1	166		T2	47		T3	13
valid_sources[0x46]	11433	1			T1	169		T2	44		T3	1
valid_sources[0x47]	13205	1			T1	174		T2	54		T3	1
valid_sources[0x48]	12568	1			T1	158		T2	64		T3	1
valid_sources[0x49]	11730	1			T1	166		T2	64		T3	3
valid_sources[0x4a]	12967	1			T1	183		T2	44		T3	2
valid_sources[0x4b]	13461	1			T1	171		T2	57		T6	15
valid_sources[0x4c]	13504	1			T1	160		T2	55		T3	2
valid_sources[0x4d]	19471	1			T1	147		T2	44		T3	4
valid_sources[0x4e]	11979	1			T1	185		T2	49		T3	2
valid_sources[0x4f]	11121	1			T1	173		T2	66		T6	3
valid_sources[0x50]	11666	1			T1	179		T2	68		T3	2
valid_sources[0x51]	12680	1			T1	158		T2	57		T3	7
valid_sources[0x52]	12855	1			T1	161		T2	45		T3	2
valid_sources[0x53]	11484	1			T1	170		T2	95		T3	1
valid_sources[0x54]	17736	1			T1	147		T2	55		T3	4
valid_sources[0x55]	12814	1			T1	154		T2	60		T3	1
valid_sources[0x56]	11733	1			T1	181		T2	74		T3	5
valid_sources[0x57]	21202	1			T1	153		T2	50		T4	6
valid_sources[0x58]	11353	1			T1	175		T2	50		T3	1
valid_sources[0x59]	12334	1			T1	145		T2	50		T3	1
valid_sources[0x5a]	11659	1			T1	154		T2	69		T6	1
valid_sources[0x5b]	11517	1			T1	130		T2	46		T3	2
valid_sources[0x5c]	17256	1			T1	179		T2	37		T3	4
valid_sources[0x5d]	12134	1			T1	167		T2	46		T3	5
valid_sources[0x5e]	18839	1			T1	153		T2	69		T3	6
valid_sources[0x5f]	12688	1			T1	167		T2	41		T6	1
valid_sources[0x60]	12595	1			T1	157		T2	49		T6	2
valid_sources[0x61]	14586	1			T1	148		T2	62		T6	7
valid_sources[0x62]	12917	1			T1	169		T2	48		T3	3
valid_sources[0x63]	22419	1			T1	148		T2	56		T3	2
valid_sources[0x64]	13556	1			T1	156		T2	63		T4	2
valid_sources[0x65]	16968	1			T1	165		T2	47		T3	1
valid_sources[0x66]	11686	1			T1	150		T2	49		T3	4
valid_sources[0x67]	11556	1			T1	166		T2	58		T3	1
valid_sources[0x68]	13885	1			T1	169		T2	57		T3	10
valid_sources[0x69]	14873	1			T1	159		T2	52		T3	1
valid_sources[0x6a]	11871	1			T1	150		T2	62		T3	4
valid_sources[0x6b]	17295	1			T1	185		T2	50		T3	3
valid_sources[0x6c]	14371	1			T1	153		T2	54		T6	24
valid_sources[0x6d]	34318	1			T1	166		T2	64		T3	5
valid_sources[0x6e]	12093	1			T1	163		T2	24		T3	8
valid_sources[0x6f]	12985	1			T1	176		T2	68		T3	1
valid_sources[0x70]	13632	1			T1	135		T2	66		T3	1
valid_sources[0x71]	12354	1			T1	159		T2	52		T6	5
valid_sources[0x72]	13405	1			T1	165		T2	46		T3	2
valid_sources[0x73]	15213	1			T1	157		T2	60		T3	1
valid_sources[0x74]	12028	1			T1	148		T2	73		T3	2
valid_sources[0x75]	12549	1			T1	152		T2	57		T3	2
valid_sources[0x76]	12106	1			T1	157		T2	55		T6	1
valid_sources[0x77]	13686	1			T1	161		T2	52		T3	3
valid_sources[0x78]	11729	1			T1	156		T2	39		T3	2
valid_sources[0x79]	14291	1			T1	166		T2	53		T4	4
valid_sources[0x7a]	13061	1			T1	159		T2	53		T3	3
valid_sources[0x7b]	11332	1			T1	162		T2	77		T3	1
valid_sources[0x7c]	13480	1			T1	160		T2	59		T3	5
valid_sources[0x7d]	11827	1			T1	169		T2	30		T3	5
valid_sources[0x7e]	11360	1			T1	151		T2	46		T3	3
valid_sources[0x7f]	11695	1			T1	178		T2	64		T3	1
valid_sources[0x80]	11282	1			T1	168		T2	51		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

340256

1

T1

100

T2

66

T3

114

values[0x0]

all_enables

biggest_size

147679

1

T1

21

T2

101

T3

107

values[0x1]

all_enables

biggest_size

133385

1

T1

9

T2

107

T3

117