Unified Coverage Report :: Module :: keymgr_reg_top

Module : keymgr_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.50	98.74	99.29	100.00		99.47	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_fault_err	100.00	100.00
u_alert_test_recov_operation_err	100.00	100.00
u_attest_sw_binding_0	100.00	100.00	100.00			100.00
u_attest_sw_binding_1	100.00	100.00	100.00			100.00
u_attest_sw_binding_2	100.00	100.00	100.00			100.00
u_attest_sw_binding_3	100.00	100.00	100.00			100.00
u_attest_sw_binding_4	100.00	100.00	100.00			100.00
u_attest_sw_binding_5	100.00	100.00	100.00			100.00
u_attest_sw_binding_6	100.00	100.00	100.00			100.00
u_attest_sw_binding_7	100.00	100.00	100.00			100.00
u_cfg_regwen	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_control_shadowed_cdi_sel	99.55	100.00	98.21			100.00	100.00
u_control_shadowed_dest_sel	99.55	100.00	98.21			100.00	100.00
u_control_shadowed_operation	99.55	100.00	98.21			100.00	100.00
u_debug_invalid_creator_seed	100.00	100.00	100.00			100.00
u_debug_invalid_dev_id	100.00	100.00	100.00			100.00
u_debug_invalid_digest	100.00	100.00	100.00			100.00
u_debug_invalid_health_state	100.00	100.00	100.00			100.00
u_debug_invalid_key	97.22	100.00	91.67			100.00
u_debug_invalid_key_version	100.00	100.00	100.00			100.00
u_debug_invalid_owner_seed	100.00	100.00	100.00			100.00
u_err_code_invalid_kmac_input	100.00	100.00	100.00			100.00
u_err_code_invalid_op	100.00	100.00	100.00			100.00
u_err_code_invalid_shadow_update	97.22	100.00	91.67			100.00
u_fault_status_cmd	96.30	88.89	100.00			100.00
u_fault_status_ctrl_fsm_chk	96.30	88.89	100.00			100.00
u_fault_status_ctrl_fsm_cnt	96.30	88.89	100.00			100.00
u_fault_status_ctrl_fsm_intg	96.30	88.89	100.00			100.00
u_fault_status_key_ecc	96.30	88.89	100.00			100.00
u_fault_status_kmac_done	96.30	88.89	100.00			100.00
u_fault_status_kmac_fsm	96.30	88.89	100.00			100.00
u_fault_status_kmac_op	96.30	88.89	100.00			100.00
u_fault_status_kmac_out	62.59	77.78	50.00			60.00
u_fault_status_regfile_intg	96.30	88.89	100.00			100.00
u_fault_status_reseed_cnt	96.30	88.89	100.00			100.00
u_fault_status_shadow	96.30	88.89	100.00			100.00
u_fault_status_side_ctrl_fsm	96.30	88.89	100.00			100.00
u_fault_status_side_ctrl_sel	96.30	88.89	100.00			100.00
u_intr_enable	100.00	100.00	100.00			100.00
u_intr_state	100.00	100.00	100.00			100.00
u_intr_test	100.00	100.00
u_key_version	100.00	100.00	100.00			100.00
u_max_creator_key_ver_regwen	100.00	100.00	100.00			100.00
u_max_creator_key_ver_shadowed	99.55	100.00	98.21			100.00	100.00
u_max_owner_int_key_ver_regwen	100.00	100.00	100.00			100.00
u_max_owner_int_key_ver_shadowed	99.55	100.00	98.21			100.00	100.00
u_max_owner_key_ver_regwen	100.00	100.00	100.00			100.00
u_max_owner_key_ver_shadowed	99.55	100.00	98.21			100.00	100.00
u_op_status	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_reseed_interval_regwen	100.00	100.00	100.00			100.00
u_reseed_interval_shadowed	99.55	100.00	98.21			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_salt_0	100.00	100.00	100.00			100.00
u_salt_1	100.00	100.00	100.00			100.00
u_salt_2	100.00	100.00	100.00			100.00
u_salt_3	100.00	100.00	100.00			100.00
u_salt_4	100.00	100.00	100.00			100.00
u_salt_5	100.00	100.00	100.00			100.00
u_salt_6	100.00	100.00	100.00			100.00
u_salt_7	100.00	100.00	100.00			100.00
u_sealing_sw_binding_0	100.00	100.00	100.00			100.00
u_sealing_sw_binding_1	100.00	100.00	100.00			100.00
u_sealing_sw_binding_2	100.00	100.00	100.00			100.00
u_sealing_sw_binding_3	100.00	100.00	100.00			100.00
u_sealing_sw_binding_4	100.00	100.00	100.00			100.00
u_sealing_sw_binding_5	100.00	100.00	100.00			100.00
u_sealing_sw_binding_6	100.00	100.00	100.00			100.00
u_sealing_sw_binding_7	100.00	100.00	100.00			100.00
u_sideload_clear	100.00	100.00	100.00			100.00
u_start	100.00	100.00	100.00			100.00
u_sw_binding_regwen	100.00	100.00
u_sw_share0_output_0	100.00	100.00	100.00			100.00
u_sw_share0_output_1	100.00	100.00	100.00			100.00
u_sw_share0_output_2	100.00	100.00	100.00			100.00
u_sw_share0_output_3	100.00	100.00	100.00			100.00
u_sw_share0_output_4	100.00	100.00	100.00			100.00
u_sw_share0_output_5	100.00	100.00	100.00			100.00
u_sw_share0_output_6	100.00	100.00	100.00			100.00
u_sw_share0_output_7	100.00	100.00	100.00			100.00
u_sw_share1_output_0	100.00	100.00	100.00			100.00
u_sw_share1_output_1	100.00	100.00	100.00			100.00
u_sw_share1_output_2	100.00	100.00	100.00			100.00
u_sw_share1_output_3	100.00	100.00	100.00			100.00
u_sw_share1_output_4	100.00	100.00	100.00			100.00
u_sw_share1_output_5	100.00	100.00	100.00			100.00
u_sw_share1_output_6	100.00	100.00	100.00			100.00
u_sw_share1_output_7	100.00	100.00	100.00			100.00
u_working_state	62.59	77.78	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_reg_top

	Line No.	Total	Covered	Percent
TOTAL		401	401	100.00
ALWAYS	72	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	476	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	642	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
CONT_ASSIGN	742	1	1	100.00
CONT_ASSIGN	756	1	1	100.00
CONT_ASSIGN	763	1	1	100.00
CONT_ASSIGN	795	1	1	100.00
CONT_ASSIGN	827	1	1	100.00
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	891	1	1	100.00
CONT_ASSIGN	923	1	1	100.00
CONT_ASSIGN	955	1	1	100.00
CONT_ASSIGN	987	1	1	100.00
CONT_ASSIGN	1019	1	1	100.00
CONT_ASSIGN	1051	1	1	100.00
CONT_ASSIGN	1083	1	1	100.00
CONT_ASSIGN	1115	1	1	100.00
CONT_ASSIGN	1147	1	1	100.00
CONT_ASSIGN	1179	1	1	100.00
CONT_ASSIGN	1211	1	1	100.00
CONT_ASSIGN	1243	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1307	1	1	100.00
CONT_ASSIGN	1339	1	1	100.00
CONT_ASSIGN	1371	1	1	100.00
CONT_ASSIGN	1403	1	1	100.00
CONT_ASSIGN	1435	1	1	100.00
CONT_ASSIGN	1467	1	1	100.00
CONT_ASSIGN	1499	1	1	100.00
CONT_ASSIGN	1531	1	1	100.00
CONT_ASSIGN	1590	1	1	100.00
CONT_ASSIGN	1659	1	1	100.00
CONT_ASSIGN	1728	1	1	100.00
ALWAYS	2943	64	64	100.00
CONT_ASSIGN	3009	1	1	100.00
ALWAYS	3013	1	1	100.00
CONT_ASSIGN	3080	1	1	100.00
CONT_ASSIGN	3082	1	1	100.00
CONT_ASSIGN	3083	1	1	100.00
CONT_ASSIGN	3085	1	1	100.00
CONT_ASSIGN	3086	1	1	100.00
CONT_ASSIGN	3088	1	1	100.00
CONT_ASSIGN	3089	1	1	100.00
CONT_ASSIGN	3091	1	1	100.00
CONT_ASSIGN	3093	1	1	100.00
CONT_ASSIGN	3094	1	1	100.00
CONT_ASSIGN	3095	1	1	100.00
CONT_ASSIGN	3097	1	1	100.00
CONT_ASSIGN	3098	1	1	100.00
CONT_ASSIGN	3099	1	1	100.00
CONT_ASSIGN	3101	1	1	100.00
CONT_ASSIGN	3103	1	1	100.00
CONT_ASSIGN	3105	1	1	100.00
CONT_ASSIGN	3106	1	1	100.00
CONT_ASSIGN	3108	1	1	100.00
CONT_ASSIGN	3109	1	1	100.00
CONT_ASSIGN	3111	1	1	100.00
CONT_ASSIGN	3112	1	1	100.00
CONT_ASSIGN	3113	1	1	100.00
CONT_ASSIGN	3115	1	1	100.00
CONT_ASSIGN	3116	1	1	100.00
CONT_ASSIGN	3117	1	1	100.00
CONT_ASSIGN	3119	1	1	100.00
CONT_ASSIGN	3120	1	1	100.00
CONT_ASSIGN	3122	1	1	100.00
CONT_ASSIGN	3123	1	1	100.00
CONT_ASSIGN	3125	1	1	100.00
CONT_ASSIGN	3126	1	1	100.00
CONT_ASSIGN	3128	1	1	100.00
CONT_ASSIGN	3129	1	1	100.00
CONT_ASSIGN	3131	1	1	100.00
CONT_ASSIGN	3132	1	1	100.00
CONT_ASSIGN	3134	1	1	100.00
CONT_ASSIGN	3135	1	1	100.00
CONT_ASSIGN	3137	1	1	100.00
CONT_ASSIGN	3138	1	1	100.00
CONT_ASSIGN	3140	1	1	100.00
CONT_ASSIGN	3141	1	1	100.00
CONT_ASSIGN	3143	1	1	100.00
CONT_ASSIGN	3144	1	1	100.00
CONT_ASSIGN	3146	1	1	100.00
CONT_ASSIGN	3147	1	1	100.00
CONT_ASSIGN	3149	1	1	100.00
CONT_ASSIGN	3150	1	1	100.00
CONT_ASSIGN	3152	1	1	100.00
CONT_ASSIGN	3153	1	1	100.00
CONT_ASSIGN	3155	1	1	100.00
CONT_ASSIGN	3156	1	1	100.00
CONT_ASSIGN	3158	1	1	100.00
CONT_ASSIGN	3159	1	1	100.00
CONT_ASSIGN	3161	1	1	100.00
CONT_ASSIGN	3162	1	1	100.00
CONT_ASSIGN	3164	1	1	100.00
CONT_ASSIGN	3165	1	1	100.00
CONT_ASSIGN	3167	1	1	100.00
CONT_ASSIGN	3168	1	1	100.00
CONT_ASSIGN	3170	1	1	100.00
CONT_ASSIGN	3171	1	1	100.00
CONT_ASSIGN	3173	1	1	100.00
CONT_ASSIGN	3174	1	1	100.00
CONT_ASSIGN	3176	1	1	100.00
CONT_ASSIGN	3177	1	1	100.00
CONT_ASSIGN	3179	1	1	100.00
CONT_ASSIGN	3180	1	1	100.00
CONT_ASSIGN	3182	1	1	100.00
CONT_ASSIGN	3183	1	1	100.00
CONT_ASSIGN	3185	1	1	100.00
CONT_ASSIGN	3186	1	1	100.00
CONT_ASSIGN	3188	1	1	100.00
CONT_ASSIGN	3189	1	1	100.00
CONT_ASSIGN	3191	1	1	100.00
CONT_ASSIGN	3192	1	1	100.00
CONT_ASSIGN	3194	1	1	100.00
CONT_ASSIGN	3195	1	1	100.00
CONT_ASSIGN	3197	1	1	100.00
CONT_ASSIGN	3198	1	1	100.00
CONT_ASSIGN	3199	1	1	100.00
CONT_ASSIGN	3201	1	1	100.00
CONT_ASSIGN	3202	1	1	100.00
CONT_ASSIGN	3204	1	1	100.00
CONT_ASSIGN	3205	1	1	100.00
CONT_ASSIGN	3206	1	1	100.00
CONT_ASSIGN	3208	1	1	100.00
CONT_ASSIGN	3209	1	1	100.00
CONT_ASSIGN	3211	1	1	100.00
CONT_ASSIGN	3212	1	1	100.00
CONT_ASSIGN	3213	1	1	100.00
CONT_ASSIGN	3215	1	1	100.00
CONT_ASSIGN	3216	1	1	100.00
CONT_ASSIGN	3219	1	1	100.00
CONT_ASSIGN	3222	1	1	100.00
CONT_ASSIGN	3225	1	1	100.00
CONT_ASSIGN	3228	1	1	100.00
CONT_ASSIGN	3231	1	1	100.00
CONT_ASSIGN	3234	1	1	100.00
CONT_ASSIGN	3237	1	1	100.00
CONT_ASSIGN	3240	1	1	100.00
CONT_ASSIGN	3243	1	1	100.00
CONT_ASSIGN	3246	1	1	100.00
CONT_ASSIGN	3249	1	1	100.00
CONT_ASSIGN	3252	1	1	100.00
CONT_ASSIGN	3255	1	1	100.00
CONT_ASSIGN	3258	1	1	100.00
CONT_ASSIGN	3261	1	1	100.00
CONT_ASSIGN	3264	1	1	100.00
CONT_ASSIGN	3266	1	1	100.00
CONT_ASSIGN	3267	1	1	100.00
CONT_ASSIGN	3269	1	1	100.00
CONT_ASSIGN	3271	1	1	100.00
CONT_ASSIGN	3273	1	1	100.00
CONT_ASSIGN	3274	1	1	100.00
CONT_ASSIGN	3276	1	1	100.00
CONT_ASSIGN	3278	1	1	100.00
CONT_ASSIGN	3280	1	1	100.00
CONT_ASSIGN	3282	1	1	100.00
CONT_ASSIGN	3284	1	1	100.00
CONT_ASSIGN	3286	1	1	100.00
CONT_ASSIGN	3288	1	1	100.00
ALWAYS	3292	64	64	100.00
ALWAYS	3360	89	89	100.00
ALWAYS	3649	3	3	100.00
ALWAYS	3657	3	3	100.00
CONT_ASSIGN	3665	1	1	100.00
CONT_ASSIGN	3668	1	1	100.00
CONT_ASSIGN	3677	1	1	100.00
CONT_ASSIGN	3688	1	1	100.00
CONT_ASSIGN	3696	1	1	100.00
CONT_ASSIGN	3697	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reg_top.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
72	1	1
73	1	1
74	1	1
75	1	1
			MISSING_ELSE
81	1	1
93	1	1
94	1	1
122	1	1
123	1	1
425	1	1
439	1	1
445	1	1
460	1	1
476	1	1
498	1	1
529	1	1
642	1	1
701	1	1
742	1	1
756	1	1
763	1	1
795	1	1
827	1	1
859	1	1
891	1	1
923	1	1
955	1	1
987	1	1
1019	1	1
1051	1	1
1083	1	1
1115	1	1
1147	1	1
1179	1	1
1211	1	1
1243	1	1
1275	1	1
1307	1	1
1339	1	1
1371	1	1
1403	1	1
1435	1	1
1467	1	1
1499	1	1
1531	1	1
1590	1	1
1659	1	1
1728	1	1
2943	1	1
2944	1	1
2945	1	1
2946	1	1
2947	1	1
2948	1	1
2949	1	1
2950	1	1
2951	1	1
2952	1	1
2953	1	1
2954	1	1
2955	1	1
2956	1	1
2957	1	1
2958	1	1
2959	1	1
2960	1	1
2961	1	1
2962	1	1
2963	1	1
2964	1	1
2965	1	1
2966	1	1
2967	1	1
2968	1	1
2969	1	1
2970	1	1
2971	1	1
2972	1	1
2973	1	1
2974	1	1
2975	1	1
2976	1	1
2977	1	1
2978	1	1
2979	1	1
2980	1	1
2981	1	1
2982	1	1
2983	1	1
2984	1	1
2985	1	1
2986	1	1
2987	1	1
2988	1	1
2989	1	1
2990	1	1
2991	1	1
2992	1	1
2993	1	1
2994	1	1
2995	1	1
2996	1	1
2997	1	1
2998	1	1
2999	1	1
3000	1	1
3001	1	1
3002	1	1
3003	1	1
3004	1	1
3005	1	1
3006	1	1
3009	1	1
3013	1	1
3080	1	1
3082	1	1
3083	1	1
3085	1	1
3086	1	1
3088	1	1
3089	1	1
3091	1	1
3093	1	1
3094	1	1
3095	1	1
3097	1	1
3098	1	1
3099	1	1
3101	1	1
3103	1	1
3105	1	1
3106	1	1
3108	1	1
3109	1	1
3111	1	1
3112	1	1
3113	1	1
3115	1	1
3116	1	1
3117	1	1
3119	1	1
3120	1	1
3122	1	1
3123	1	1
3125	1	1
3126	1	1
3128	1	1
3129	1	1
3131	1	1
3132	1	1
3134	1	1
3135	1	1
3137	1	1
3138	1	1
3140	1	1
3141	1	1
3143	1	1
3144	1	1
3146	1	1
3147	1	1
3149	1	1
3150	1	1
3152	1	1
3153	1	1
3155	1	1
3156	1	1
3158	1	1
3159	1	1
3161	1	1
3162	1	1
3164	1	1
3165	1	1
3167	1	1
3168	1	1
3170	1	1
3171	1	1
3173	1	1
3174	1	1
3176	1	1
3177	1	1
3179	1	1
3180	1	1
3182	1	1
3183	1	1
3185	1	1
3186	1	1
3188	1	1
3189	1	1
3191	1	1
3192	1	1
3194	1	1
3195	1	1
3197	1	1
3198	1	1
3199	1	1
3201	1	1
3202	1	1
3204	1	1
3205	1	1
3206	1	1
3208	1	1
3209	1	1
3211	1	1
3212	1	1
3213	1	1
3215	1	1
3216	1	1
3219	1	1
3222	1	1
3225	1	1
3228	1	1
3231	1	1
3234	1	1
3237	1	1
3240	1	1
3243	1	1
3246	1	1
3249	1	1
3252	1	1
3255	1	1
3258	1	1
3261	1	1
3264	1	1
3266	1	1
3267	1	1
3269	1	1
3271	1	1
3273	1	1
3274	1	1
3276	1	1
3278	1	1
3280	1	1
3282	1	1
3284	1	1
3286	1	1
3288	1	1
3292	1	1
3293	1	1
3294	1	1
3295	1	1
3296	1	1
3297	1	1
3298	1	1
3299	1	1
3300	1	1
3301	1	1
3302	1	1
3303	1	1
3304	1	1
3305	1	1
3306	1	1
3307	1	1
3308	1	1
3309	1	1
3310	1	1
3311	1	1
3312	1	1
3313	1	1
3314	1	1
3315	1	1
3316	1	1
3317	1	1
3318	1	1
3319	1	1
3320	1	1
3321	1	1
3322	1	1
3323	1	1
3324	1	1
3325	1	1
3326	1	1
3327	1	1
3328	1	1
3329	1	1
3330	1	1
3331	1	1
3332	1	1
3333	1	1
3334	1	1
3335	1	1
3336	1	1
3337	1	1
3338	1	1
3339	1	1
3340	1	1
3341	1	1
3342	1	1
3343	1	1
3344	1	1
3345	1	1
3346	1	1
3347	1	1
3348	1	1
3349	1	1
3350	1	1
3351	1	1
3352	1	1
3353	1	1
3354	1	1
3355	1	1
3360	1	1
3361	1	1
3363	1	1
3367	1	1
3371	1	1
3375	1	1
3376	1	1
3380	1	1
3384	1	1
3388	1	1
3389	1	1
3390	1	1
3394	1	1
3398	1	1
3402	1	1
3406	1	1
3410	1	1
3414	1	1
3418	1	1
3422	1	1
3426	1	1
3430	1	1
3434	1	1
3438	1	1
3442	1	1
3446	1	1
3450	1	1
3454	1	1
3458	1	1
3462	1	1
3466	1	1
3470	1	1
3474	1	1
3478	1	1
3482	1	1
3486	1	1
3490	1	1
3494	1	1
3498	1	1
3502	1	1
3506	1	1
3510	1	1
3514	1	1
3518	1	1
3522	1	1
3526	1	1
3530	1	1
3534	1	1
3538	1	1
3542	1	1
3546	1	1
3550	1	1
3554	1	1
3558	1	1
3562	1	1
3566	1	1
3570	1	1
3574	1	1
3578	1	1
3582	1	1
3586	1	1
3590	1	1
3594	1	1
3598	1	1
3602	1	1
3606	1	1
3607	1	1
3608	1	1
3612	1	1
3613	1	1
3614	1	1
3615	1	1
3616	1	1
3617	1	1
3618	1	1
3619	1	1
3620	1	1
3621	1	1
3622	1	1
3623	1	1
3624	1	1
3625	1	1
3629	1	1
3630	1	1
3631	1	1
3632	1	1
3633	1	1
3634	1	1
3635	1	1
3649	1	1
3650	1	1
3652	1	1
3657	1	1
3658	1	1
3660	1	1
3665	1	1
3668	1	1
3677	1	1
3688	1	1
3696	1	1
3697	1	1

---

Cond Coverage for Module : keymgr_reg_top

	Total	Covered	Percent
Conditions	768	768	100.00
Logical	768	768	100.00
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
62-3013	100.00
3013-3665	100.00

---

Branch Coverage for Module : keymgr_reg_top

	Line No.	Total	Covered	Percent
Branches		73	73	100.00
TERNARY	3009	2	2	100.00
IF	72	3	3	100.00
CASE	3361	64	64	100.00
IF	3649	2	2	100.00
IF	3657	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reg_top.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	3009	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	72	if ((!rst_ni))
-2-:	74	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T38,T11,T42
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3361	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
addr_hit[38]	Covered	T1,T2,T3
addr_hit[39]	Covered	T1,T2,T3
addr_hit[40]	Covered	T1,T2,T3
addr_hit[41]	Covered	T1,T2,T3
addr_hit[42]	Covered	T1,T2,T3
addr_hit[43]	Covered	T1,T2,T3
addr_hit[44]	Covered	T1,T2,T3
addr_hit[45]	Covered	T1,T2,T3
addr_hit[46]	Covered	T1,T2,T3
addr_hit[47]	Covered	T1,T2,T3
addr_hit[48]	Covered	T1,T2,T3
addr_hit[49]	Covered	T1,T2,T3
addr_hit[50]	Covered	T1,T2,T3
addr_hit[51]	Covered	T1,T2,T3
addr_hit[52]	Covered	T1,T2,T3
addr_hit[53]	Covered	T1,T2,T3
addr_hit[54]	Covered	T1,T2,T3
addr_hit[55]	Covered	T1,T2,T3
addr_hit[56]	Covered	T1,T2,T3
addr_hit[57]	Covered	T1,T2,T3
addr_hit[58]	Covered	T1,T2,T3
addr_hit[59]	Covered	T1,T2,T3
addr_hit[60]	Covered	T1,T2,T3
addr_hit[61]	Covered	T1,T2,T3
addr_hit[62]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3649	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3657	if ((!rst_shadowed_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	24269444	3704449	0	0
reAfterRv	24269444	3704449	0	0
rePulse	24269444	3314988	0	0
wePulse	24269444	389461	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	24269444	3704449	0	0
T1	133580	41464	0	0
T2	82724	14131	0	0
T3	6098	656	0	0
T4	10969	1198	0	0
T5	7988	921	0	0
T6	5692	645	0	0
T14	957	7	0	0
T15	11443	888	0	0
T16	9345	931	0	0
T17	10583	893	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	24269444	3704449	0	0
T1	133580	41464	0	0
T2	82724	14131	0	0
T3	6098	656	0	0
T4	10969	1198	0	0
T5	7988	921	0	0
T6	5692	645	0	0
T14	957	7	0	0
T15	11443	888	0	0
T16	9345	931	0	0
T17	10583	893	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	24269444	3314988	0	0
T1	133580	41383	0	0
T2	82724	13852	0	0
T3	6098	351	0	0
T4	10969	1092	0	0
T5	7988	602	0	0
T6	5692	460	0	0
T14	957	1	0	0
T15	11443	564	0	0
T16	9345	508	0	0
T17	10583	669	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	24269444	389461	0	0
T1	133580	81	0	0
T2	82724	279	0	0
T3	6098	305	0	0
T4	10969	106	0	0
T5	7988	319	0	0
T6	5692	185	0	0
T14	957	6	0	0
T15	11443	324	0	0
T16	9345	423	0	0
T17	10583	224	0	0