Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
22567692 |
22410400 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22567692 |
22410400 |
0 |
0 |
T1 |
133580 |
133497 |
0 |
0 |
T2 |
82724 |
82650 |
0 |
0 |
T3 |
6098 |
6032 |
0 |
0 |
T4 |
10969 |
10909 |
0 |
0 |
T5 |
7988 |
7927 |
0 |
0 |
T6 |
5692 |
5613 |
0 |
0 |
T14 |
957 |
883 |
0 |
0 |
T15 |
11443 |
11392 |
0 |
0 |
T16 |
9345 |
9215 |
0 |
0 |
T17 |
10583 |
10505 |
0 |
0 |