Module Definition
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Module : keymgr_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.keymgr_csr_assert 100.00 100.00


Module Instance : tb.dut.keymgr_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : keymgr_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 32 32 100.00 32 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 32 32 100.00 32 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 24269444 14702 0 0
attest_sw_binding_0_rd_A 24269444 3291 0 0
attest_sw_binding_1_rd_A 24269444 3189 0 0
attest_sw_binding_2_rd_A 24269444 2870 0 0
attest_sw_binding_3_rd_A 24269444 2918 0 0
attest_sw_binding_4_rd_A 24269444 3148 0 0
attest_sw_binding_5_rd_A 24269444 3211 0 0
attest_sw_binding_6_rd_A 24269444 3265 0 0
attest_sw_binding_7_rd_A 24269444 2993 0 0
intr_enable_rd_A 24269444 3786 0 0
key_version_rd_A 24269444 3045 0 0
max_creator_key_ver_regwen_rd_A 24269444 3228 0 0
max_owner_int_key_ver_regwen_rd_A 24269444 3218 0 0
max_owner_key_ver_regwen_rd_A 24269444 3296 0 0
reseed_interval_regwen_rd_A 24269444 3268 0 0
salt_0_rd_A 24269444 3121 0 0
salt_1_rd_A 24269444 3124 0 0
salt_2_rd_A 24269444 3075 0 0
salt_3_rd_A 24269444 3037 0 0
salt_4_rd_A 24269444 3243 0 0
salt_5_rd_A 24269444 3069 0 0
salt_6_rd_A 24269444 3262 0 0
salt_7_rd_A 24269444 3193 0 0
sealing_sw_binding_0_rd_A 24269444 3181 0 0
sealing_sw_binding_1_rd_A 24269444 3350 0 0
sealing_sw_binding_2_rd_A 24269444 3084 0 0
sealing_sw_binding_3_rd_A 24269444 3064 0 0
sealing_sw_binding_4_rd_A 24269444 3247 0 0
sealing_sw_binding_5_rd_A 24269444 3087 0 0
sealing_sw_binding_6_rd_A 24269444 3029 0 0
sealing_sw_binding_7_rd_A 24269444 3182 0 0
sideload_clear_rd_A 24269444 3157 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 14702 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T54 0 488 0 0
T58 0 203 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 233 0 0
T104 0 752 0 0
T117 0 549 0 0
T118 0 424 0 0
T119 0 54 0 0
T120 0 200 0 0
T121 0 288 0 0
T127 835 0 0 0
T151 0 67 0 0

attest_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3291 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 35 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 32 0 0
T121 0 41 0 0
T127 835 0 0 0
T133 0 41 0 0
T134 0 21 0 0
T152 0 23 0 0
T153 0 29 0 0
T154 0 40 0 0
T155 0 21 0 0
T156 0 178 0 0

attest_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3189 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 25 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 23 0 0
T121 0 55 0 0
T127 835 0 0 0
T133 0 34 0 0
T134 0 14 0 0
T152 0 26 0 0
T153 0 20 0 0
T154 0 22 0 0
T155 0 17 0 0
T156 0 247 0 0

attest_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 2870 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 39 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 16 0 0
T121 0 81 0 0
T127 835 0 0 0
T133 0 27 0 0
T152 0 34 0 0
T153 0 24 0 0
T154 0 21 0 0
T155 0 16 0 0
T156 0 189 0 0
T157 0 5 0 0

attest_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 2918 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 63 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 40 0 0
T121 0 62 0 0
T127 835 0 0 0
T133 0 28 0 0
T152 0 23 0 0
T153 0 22 0 0
T154 0 40 0 0
T155 0 30 0 0
T156 0 224 0 0
T157 0 4 0 0

attest_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3148 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 36 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 29 0 0
T121 0 33 0 0
T127 835 0 0 0
T133 0 10 0 0
T152 0 39 0 0
T153 0 16 0 0
T154 0 34 0 0
T155 0 24 0 0
T156 0 202 0 0
T157 0 9 0 0

attest_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3211 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 34 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 44 0 0
T121 0 72 0 0
T127 835 0 0 0
T133 0 36 0 0
T152 0 22 0 0
T153 0 8 0 0
T154 0 43 0 0
T155 0 12 0 0
T156 0 215 0 0
T157 0 16 0 0

attest_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3265 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 36 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 22 0 0
T121 0 40 0 0
T127 835 0 0 0
T133 0 38 0 0
T152 0 15 0 0
T153 0 26 0 0
T154 0 17 0 0
T155 0 27 0 0
T156 0 223 0 0
T157 0 17 0 0

attest_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 2993 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 51 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 19 0 0
T121 0 61 0 0
T127 835 0 0 0
T133 0 32 0 0
T134 0 46 0 0
T152 0 27 0 0
T153 0 48 0 0
T154 0 37 0 0
T155 0 10 0 0
T156 0 187 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3786 0 0
T8 0 52 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T47 0 23 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 44 0 0
T76 0 28 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 74 0 0
T121 0 36 0 0
T127 835 0 0 0
T158 0 38 0 0
T159 0 31 0 0
T160 0 21 0 0
T161 0 20 0 0

key_version_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3045 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 26 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 32 0 0
T121 0 37 0 0
T127 835 0 0 0
T133 0 43 0 0
T152 0 30 0 0
T153 0 22 0 0
T154 0 15 0 0
T155 0 15 0 0
T156 0 214 0 0
T157 0 4 0 0

max_creator_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3228 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 20 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 28 0 0
T121 0 66 0 0
T127 835 0 0 0
T133 0 18 0 0
T152 0 23 0 0
T153 0 34 0 0
T154 0 22 0 0
T155 0 18 0 0
T156 0 226 0 0
T157 0 18 0 0

max_owner_int_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3218 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 39 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 37 0 0
T121 0 64 0 0
T127 835 0 0 0
T133 0 8 0 0
T152 0 55 0 0
T153 0 54 0 0
T154 0 19 0 0
T155 0 17 0 0
T156 0 217 0 0
T162 0 5 0 0

max_owner_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3296 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 42 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 33 0 0
T121 0 56 0 0
T127 835 0 0 0
T133 0 83 0 0
T152 0 43 0 0
T153 0 27 0 0
T154 0 16 0 0
T155 0 15 0 0
T156 0 268 0 0
T157 0 13 0 0

reseed_interval_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3268 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 25 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 22 0 0
T121 0 38 0 0
T127 835 0 0 0
T133 0 49 0 0
T152 0 35 0 0
T153 0 31 0 0
T154 0 36 0 0
T155 0 20 0 0
T156 0 220 0 0
T157 0 8 0 0

salt_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3121 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 46 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 30 0 0
T121 0 61 0 0
T127 835 0 0 0
T133 0 36 0 0
T152 0 24 0 0
T153 0 12 0 0
T154 0 21 0 0
T155 0 19 0 0
T156 0 234 0 0
T157 0 18 0 0

salt_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3124 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 26 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 42 0 0
T121 0 64 0 0
T127 835 0 0 0
T133 0 69 0 0
T152 0 25 0 0
T153 0 26 0 0
T154 0 20 0 0
T155 0 15 0 0
T156 0 190 0 0
T157 0 7 0 0

salt_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3075 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 24 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 43 0 0
T121 0 85 0 0
T127 835 0 0 0
T133 0 41 0 0
T152 0 27 0 0
T153 0 12 0 0
T154 0 28 0 0
T155 0 19 0 0
T156 0 210 0 0
T157 0 6 0 0

salt_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3037 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 41 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 29 0 0
T121 0 55 0 0
T127 835 0 0 0
T133 0 49 0 0
T152 0 20 0 0
T153 0 26 0 0
T154 0 4 0 0
T155 0 7 0 0
T156 0 209 0 0
T157 0 15 0 0

salt_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3243 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 31 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 23 0 0
T121 0 58 0 0
T127 835 0 0 0
T133 0 61 0 0
T152 0 27 0 0
T153 0 9 0 0
T154 0 24 0 0
T155 0 11 0 0
T156 0 171 0 0
T157 0 3 0 0

salt_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3069 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 57 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 20 0 0
T121 0 68 0 0
T127 835 0 0 0
T133 0 56 0 0
T152 0 47 0 0
T153 0 30 0 0
T154 0 17 0 0
T155 0 17 0 0
T156 0 216 0 0
T157 0 1 0 0

salt_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3262 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 47 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 21 0 0
T121 0 50 0 0
T127 835 0 0 0
T133 0 44 0 0
T152 0 21 0 0
T153 0 27 0 0
T154 0 25 0 0
T155 0 23 0 0
T156 0 225 0 0
T157 0 7 0 0

salt_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3193 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 47 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 44 0 0
T121 0 54 0 0
T127 835 0 0 0
T133 0 52 0 0
T152 0 38 0 0
T153 0 30 0 0
T154 0 17 0 0
T155 0 16 0 0
T156 0 226 0 0
T157 0 19 0 0

sealing_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3181 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 23 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 24 0 0
T121 0 89 0 0
T127 835 0 0 0
T133 0 65 0 0
T152 0 35 0 0
T153 0 33 0 0
T154 0 26 0 0
T155 0 32 0 0
T156 0 200 0 0
T157 0 1 0 0

sealing_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3350 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 24 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 21 0 0
T121 0 74 0 0
T127 835 0 0 0
T133 0 77 0 0
T152 0 34 0 0
T153 0 26 0 0
T154 0 32 0 0
T155 0 9 0 0
T156 0 219 0 0
T157 0 12 0 0

sealing_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3084 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 21 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 27 0 0
T121 0 71 0 0
T127 835 0 0 0
T133 0 36 0 0
T152 0 23 0 0
T153 0 29 0 0
T154 0 35 0 0
T155 0 17 0 0
T156 0 235 0 0
T157 0 5 0 0

sealing_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3064 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 31 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 32 0 0
T121 0 52 0 0
T127 835 0 0 0
T133 0 39 0 0
T152 0 19 0 0
T153 0 16 0 0
T154 0 25 0 0
T155 0 24 0 0
T156 0 206 0 0
T157 0 25 0 0

sealing_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3247 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 46 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 30 0 0
T121 0 90 0 0
T127 835 0 0 0
T133 0 69 0 0
T152 0 40 0 0
T153 0 27 0 0
T154 0 29 0 0
T155 0 18 0 0
T156 0 238 0 0
T157 0 7 0 0

sealing_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3087 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 32 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 62 0 0
T121 0 60 0 0
T127 835 0 0 0
T133 0 39 0 0
T152 0 32 0 0
T153 0 18 0 0
T154 0 11 0 0
T155 0 6 0 0
T156 0 238 0 0
T157 0 10 0 0

sealing_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3029 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 22 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 30 0 0
T121 0 55 0 0
T127 835 0 0 0
T133 0 55 0 0
T134 0 31 0 0
T152 0 32 0 0
T153 0 15 0 0
T154 0 28 0 0
T155 0 12 0 0
T156 0 217 0 0

sealing_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3182 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 16 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 43 0 0
T121 0 63 0 0
T127 835 0 0 0
T133 0 67 0 0
T152 0 32 0 0
T153 0 38 0 0
T154 0 33 0 0
T155 0 12 0 0
T156 0 198 0 0
T157 0 8 0 0

sideload_clear_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24269444 3157 0 0
T11 48158 0 0 0
T42 31562 0 0 0
T51 7162 0 0 0
T52 7745 0 0 0
T58 0 39 0 0
T80 10633 0 0 0
T81 5700 0 0 0
T82 65107 0 0 0
T99 1112 0 0 0
T100 23705 35 0 0
T121 0 47 0 0
T127 835 0 0 0
T133 0 51 0 0
T152 0 24 0 0
T153 0 44 0 0
T154 0 26 0 0
T155 0 17 0 0
T156 0 198 0 0
T157 0 21 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%