Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3285433	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

588304

1

T1

170

T2

169

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3479851	1			T1	349		T2	612		T3	1
values[0x0]	195276	1			T1	51		T2	41		T3	2
values[0x1]	198610	1			T1	56		T2	47		T14	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2246293	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1627444

1

T1

238

T2

313

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12152	1			T4	21		T17	2		T5	76
valid_sources[0x01]	13005	1			T4	9		T17	2		T5	46
valid_sources[0x02]	9972	1			T4	28		T17	1		T5	142
valid_sources[0x03]	10674	1			T4	48		T17	2		T5	87
valid_sources[0x04]	10170	1			T4	28		T17	3		T5	68
valid_sources[0x05]	10088	1			T4	23		T17	1		T5	97
valid_sources[0x06]	16006	1			T4	23		T17	1		T5	58
valid_sources[0x07]	9527	1			T4	21		T17	8		T5	67
valid_sources[0x08]	10537	1			T4	31		T17	2		T5	58
valid_sources[0x09]	10763	1			T4	8		T17	3		T5	114
valid_sources[0x0a]	15360	1			T14	2		T4	18		T17	4
valid_sources[0x0b]	9110	1			T4	18		T17	4		T5	41
valid_sources[0x0c]	9819	1			T4	26		T17	2		T5	81
valid_sources[0x0d]	12501	1			T4	40		T5	52		T18	5
valid_sources[0x0e]	24149	1			T4	18		T17	3		T5	81
valid_sources[0x0f]	13333	1			T4	17		T17	1		T5	52
valid_sources[0x10]	10150	1			T4	27		T17	1		T5	52
valid_sources[0x11]	11224	1			T4	20		T17	1		T5	47
valid_sources[0x12]	9631	1			T4	27		T17	1		T5	102
valid_sources[0x13]	9452	1			T4	43		T17	2		T5	26
valid_sources[0x14]	14509	1			T4	26		T16	3		T17	2
valid_sources[0x15]	9971	1			T4	42		T17	3		T5	50
valid_sources[0x16]	11781	1			T4	4		T17	4		T5	80
valid_sources[0x17]	10262	1			T4	48		T17	3		T5	22
valid_sources[0x18]	10349	1			T4	28		T17	1		T5	36
valid_sources[0x19]	12299	1			T4	23		T17	3		T5	72
valid_sources[0x1a]	9490	1			T4	2		T17	3		T5	32
valid_sources[0x1b]	10133	1			T4	16		T17	6		T5	47
valid_sources[0x1c]	18854	1			T4	46		T17	1		T5	102
valid_sources[0x1d]	9612	1			T4	29		T17	2		T5	117
valid_sources[0x1e]	10613	1			T4	24		T17	4		T5	59
valid_sources[0x1f]	11364	1			T4	24		T17	4		T5	27
valid_sources[0x20]	11241	1			T4	13		T17	4		T5	91
valid_sources[0x21]	9774	1			T4	1		T17	1		T5	86
valid_sources[0x22]	9919	1			T4	23		T17	5		T5	87
valid_sources[0x23]	13532	1			T4	8		T17	3		T5	50
valid_sources[0x24]	12418	1			T4	5		T17	5		T5	81
valid_sources[0x25]	13573	1			T4	26		T5	54		T40	2
valid_sources[0x26]	10304	1			T4	38		T17	8		T5	69
valid_sources[0x27]	9892	1			T4	37		T17	1		T5	34
valid_sources[0x28]	9362	1			T4	15		T5	37		T40	1
valid_sources[0x29]	9643	1			T3	3		T4	29		T17	2
valid_sources[0x2a]	9466	1			T4	25		T17	3		T5	62
valid_sources[0x2b]	9848	1			T4	10		T17	3		T5	50
valid_sources[0x2c]	10166	1			T4	38		T17	3		T5	66
valid_sources[0x2d]	11510	1			T14	1		T4	22		T17	5
valid_sources[0x2e]	10062	1			T4	27		T17	4		T5	62
valid_sources[0x2f]	9191	1			T4	15		T17	2		T5	86
valid_sources[0x30]	19778	1			T4	45		T17	1		T5	25
valid_sources[0x31]	10030	1			T4	22		T17	3		T5	81
valid_sources[0x32]	9812	1			T4	7		T17	3		T5	72
valid_sources[0x33]	9288	1			T4	18		T17	5		T5	52
valid_sources[0x34]	15968	1			T4	7		T17	2		T5	84
valid_sources[0x35]	19188	1			T4	28		T17	2		T5	42
valid_sources[0x36]	9509	1			T4	33		T17	3		T5	83
valid_sources[0x37]	9728	1			T4	15		T17	2		T5	54
valid_sources[0x38]	353880	1			T4	6		T17	3		T5	72
valid_sources[0x39]	13183	1			T4	18		T17	5		T5	50
valid_sources[0x3a]	9660	1			T14	4		T4	5		T17	4
valid_sources[0x3b]	9465	1			T4	14		T17	6		T5	84
valid_sources[0x3c]	11628	1			T4	29		T17	3		T5	68
valid_sources[0x3d]	11118	1			T4	13		T17	1		T5	53
valid_sources[0x3e]	16305	1			T4	30		T5	70		T18	2
valid_sources[0x3f]	26125	1			T4	16		T17	3		T5	91
valid_sources[0x40]	11075	1			T4	20		T5	68		T18	7
valid_sources[0x41]	10258	1			T4	27		T17	5		T5	79
valid_sources[0x42]	15408	1			T4	7		T17	3		T5	120
valid_sources[0x43]	11811	1			T14	3		T4	31		T17	3
valid_sources[0x44]	9657	1			T4	26		T5	58		T18	2
valid_sources[0x45]	12273	1			T4	17		T17	1		T5	86
valid_sources[0x46]	12937	1			T4	26		T5	84		T18	3
valid_sources[0x47]	9954	1			T4	19		T17	3		T5	48
valid_sources[0x48]	24927	1			T4	19		T17	2		T5	79
valid_sources[0x49]	16195	1			T4	14		T17	2		T5	81
valid_sources[0x4a]	10632	1			T4	6		T17	2		T5	91
valid_sources[0x4b]	9744	1			T4	24		T17	1		T5	87
valid_sources[0x4c]	9176	1			T4	12		T17	3		T5	49
valid_sources[0x4d]	9827	1			T4	3		T17	1		T5	38
valid_sources[0x4e]	9532	1			T4	9		T17	2		T5	83
valid_sources[0x4f]	9736	1			T4	23		T17	3		T5	27
valid_sources[0x50]	9234	1			T4	28		T17	1		T5	38
valid_sources[0x51]	11500	1			T4	32		T17	1		T5	96
valid_sources[0x52]	27213	1			T14	1		T4	22		T17	1
valid_sources[0x53]	12202	1			T4	42		T17	1		T5	61
valid_sources[0x54]	10011	1			T4	18		T17	6		T5	56
valid_sources[0x55]	11392	1			T4	37		T17	2		T5	38
valid_sources[0x56]	13855	1			T4	29		T17	3		T5	59
valid_sources[0x57]	9608	1			T4	40		T17	2		T5	41
valid_sources[0x58]	14605	1			T4	24		T17	4		T5	75
valid_sources[0x59]	9763	1			T4	11		T17	6		T5	73
valid_sources[0x5a]	9624	1			T4	27		T17	2		T5	96
valid_sources[0x5b]	10401	1			T4	8		T5	41		T18	3
valid_sources[0x5c]	9553	1			T4	16		T17	4		T5	30
valid_sources[0x5d]	15413	1			T4	35		T17	3		T5	55
valid_sources[0x5e]	25130	1			T4	6		T17	5		T5	51
valid_sources[0x5f]	11708	1			T4	21		T5	49		T18	5
valid_sources[0x60]	10046	1			T4	27		T17	1		T5	67
valid_sources[0x61]	10752	1			T2	700		T4	15		T17	5
valid_sources[0x62]	13427	1			T4	23		T5	62		T18	2
valid_sources[0x63]	33513	1			T4	24		T17	4		T5	66
valid_sources[0x64]	9948	1			T4	22		T17	2		T5	79
valid_sources[0x65]	9577	1			T4	8		T17	2		T5	42
valid_sources[0x66]	9726	1			T4	16		T17	3		T5	99
valid_sources[0x67]	10748	1			T4	60		T17	3		T5	70
valid_sources[0x68]	9973	1			T4	47		T17	3		T5	54
valid_sources[0x69]	63178	1			T4	36		T5	60		T18	2
valid_sources[0x6a]	10171	1			T4	58		T17	2		T5	55
valid_sources[0x6b]	11733	1			T4	26		T17	7		T5	62
valid_sources[0x6c]	25941	1			T4	25		T17	6		T5	62
valid_sources[0x6d]	12178	1			T4	19		T17	6		T5	45
valid_sources[0x6e]	10938	1			T4	21		T17	4		T5	51
valid_sources[0x6f]	42046	1			T4	25		T17	11		T5	63
valid_sources[0x70]	9681	1			T4	45		T17	2		T5	72
valid_sources[0x71]	10248	1			T4	25		T17	6		T5	42
valid_sources[0x72]	10154	1			T4	11		T17	2		T5	106
valid_sources[0x73]	10006	1			T4	22		T17	5		T5	77
valid_sources[0x74]	9752	1			T4	21		T5	94		T18	1
valid_sources[0x75]	9877	1			T4	52		T17	1		T5	84
valid_sources[0x76]	9587	1			T4	25		T17	2		T5	102
valid_sources[0x77]	26602	1			T4	5		T17	1		T5	25
valid_sources[0x78]	9782	1			T4	14		T17	6		T5	71
valid_sources[0x79]	11202	1			T4	5		T17	2		T5	66
valid_sources[0x7a]	10899	1			T4	23		T17	4		T5	104
valid_sources[0x7b]	20819	1			T4	23		T16	4		T17	1
valid_sources[0x7c]	11537	1			T4	10		T17	6		T5	42
valid_sources[0x7d]	10582	1			T4	8		T17	5		T5	86
valid_sources[0x7e]	9569	1			T4	18		T17	3		T5	55
valid_sources[0x7f]	10091	1			T14	3		T4	6		T5	69
valid_sources[0x80]	10089	1			T4	6		T17	1		T5	29

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

321408

1

T1

136

T2

142

T3

1

values[0x0]

all_enables

biggest_size

140637

1

T1

22

T2

17

T3

1

values[0x1]

all_enables

biggest_size

126259

1

T1

12

T2

10

T14

4