Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22945202	16645	0	0
attest_sw_binding_0_rd_A	22945202	2734	0	0
attest_sw_binding_1_rd_A	22945202	2871	0	0
attest_sw_binding_2_rd_A	22945202	2608	0	0
attest_sw_binding_3_rd_A	22945202	2708	0	0
attest_sw_binding_4_rd_A	22945202	2868	0	0
attest_sw_binding_5_rd_A	22945202	2753	0	0
attest_sw_binding_6_rd_A	22945202	2764	0	0
attest_sw_binding_7_rd_A	22945202	2796	0	0
intr_enable_rd_A	22945202	3337	0	0
key_version_rd_A	22945202	2648	0	0
max_creator_key_ver_regwen_rd_A	22945202	2801	0	0
max_owner_int_key_ver_regwen_rd_A	22945202	2751	0	0
max_owner_key_ver_regwen_rd_A	22945202	2827	0	0
reseed_interval_regwen_rd_A	22945202	2747	0	0
salt_0_rd_A	22945202	2647	0	0
salt_1_rd_A	22945202	2601	0	0
salt_2_rd_A	22945202	2607	0	0
salt_3_rd_A	22945202	2707	0	0
salt_4_rd_A	22945202	2559	0	0
salt_5_rd_A	22945202	2651	0	0
salt_6_rd_A	22945202	2606	0	0
salt_7_rd_A	22945202	2541	0	0
sealing_sw_binding_0_rd_A	22945202	2845	0	0
sealing_sw_binding_1_rd_A	22945202	2762	0	0
sealing_sw_binding_2_rd_A	22945202	3004	0	0
sealing_sw_binding_3_rd_A	22945202	2716	0	0
sealing_sw_binding_4_rd_A	22945202	2693	0	0
sealing_sw_binding_5_rd_A	22945202	2458	0	0
sealing_sw_binding_6_rd_A	22945202	2788	0	0
sealing_sw_binding_7_rd_A	22945202	2690	0	0
sideload_clear_rd_A	22945202	2883	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	16645	0	0
T21	1603	0	0	0
T62	6203	0	0	0
T66	9860	0	0	0
T71	4442	0	0	0
T72	25662	0	0	0
T73	7870	0	0	0
T74	17797	285	0	0
T81	0	1006	0	0
T104	4370	0	0	0
T113	35168	0	0	0
T124	17957	47	0	0
T126	0	555	0	0
T137	0	59	0	0
T138	0	986	0	0
T139	0	146	0	0
T140	0	37	0	0
T141	0	723	0	0
T143	0	508	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2734	0	0
T127	0	193	0	0
T137	36874	38	0	0
T139	0	30	0	0
T140	0	16	0	0
T158	0	5	0	0
T161	0	7	0	0
T172	0	89	0	0
T178	0	40	0	0
T195	0	58	0	0
T196	0	6	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2871	0	0
T127	0	188	0	0
T137	36874	28	0	0
T139	0	51	0	0
T140	0	22	0	0
T158	0	55	0	0
T161	0	2	0	0
T172	0	66	0	0
T178	0	46	0	0
T195	0	38	0	0
T196	0	9	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2608	0	0
T127	0	165	0	0
T137	36874	18	0	0
T139	0	26	0	0
T140	0	14	0	0
T158	0	24	0	0
T161	0	4	0	0
T172	0	56	0	0
T178	0	29	0	0
T195	0	57	0	0
T196	0	7	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2708	0	0
T127	0	201	0	0
T137	36874	33	0	0
T139	0	48	0	0
T140	0	23	0	0
T158	0	11	0	0
T161	0	4	0	0
T172	0	87	0	0
T178	0	63	0	0
T195	0	80	0	0
T196	0	4	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2868	0	0
T127	0	193	0	0
T137	36874	23	0	0
T139	0	46	0	0
T140	0	27	0	0
T158	0	35	0	0
T161	0	2	0	0
T172	0	91	0	0
T178	0	42	0	0
T195	0	58	0	0
T196	0	12	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2753	0	0
T127	0	199	0	0
T137	36874	10	0	0
T139	0	30	0	0
T140	0	36	0	0
T158	0	39	0	0
T172	0	97	0	0
T178	0	44	0	0
T195	0	39	0	0
T196	0	16	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0
T206	0	4	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2764	0	0
T127	0	215	0	0
T137	36874	51	0	0
T139	0	37	0	0
T140	0	16	0	0
T158	0	14	0	0
T161	0	8	0	0
T172	0	87	0	0
T178	0	47	0	0
T195	0	86	0	0
T196	0	9	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2796	0	0
T127	0	212	0	0
T137	36874	23	0	0
T139	0	27	0	0
T140	0	24	0	0
T158	0	69	0	0
T161	0	4	0	0
T172	0	90	0	0
T178	0	60	0	0
T195	0	71	0	0
T196	0	5	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	3337	0	0
T44	3621	0	0	0
T51	65714	45	0	0
T58	10824	0	0	0
T67	9950	0	0	0
T75	3405	0	0	0
T77	0	12	0	0
T113	0	8	0	0
T137	0	41	0	0
T139	0	61	0	0
T140	0	55	0	0
T207	0	44	0	0
T208	0	9	0	0
T209	0	39	0	0
T210	0	21	0	0
T211	52774	0	0	0
T212	3771	0	0	0
T213	10502	0	0	0
T214	9996	0	0	0
T215	3814	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2648	0	0
T127	0	200	0	0
T137	36874	8	0	0
T139	0	36	0	0
T140	0	41	0	0
T158	0	28	0	0
T161	0	1	0	0
T172	0	83	0	0
T178	0	15	0	0
T195	0	61	0	0
T196	0	6	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2801	0	0
T127	0	184	0	0
T137	36874	39	0	0
T139	0	39	0	0
T140	0	27	0	0
T158	0	14	0	0
T161	0	7	0	0
T172	0	66	0	0
T178	0	36	0	0
T195	0	80	0	0
T196	0	9	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2751	0	0
T127	0	221	0	0
T137	36874	21	0	0
T139	0	36	0	0
T140	0	18	0	0
T158	0	20	0	0
T161	0	7	0	0
T172	0	76	0	0
T178	0	55	0	0
T195	0	49	0	0
T196	0	14	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2827	0	0
T127	0	180	0	0
T137	36874	30	0	0
T139	0	50	0	0
T140	0	18	0	0
T158	0	71	0	0
T161	0	4	0	0
T172	0	76	0	0
T178	0	33	0	0
T195	0	62	0	0
T196	0	6	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2747	0	0
T127	0	217	0	0
T137	36874	26	0	0
T139	0	39	0	0
T140	0	18	0	0
T158	0	9	0	0
T161	0	2	0	0
T172	0	92	0	0
T178	0	19	0	0
T195	0	48	0	0
T196	0	4	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2647	0	0
T127	0	209	0	0
T137	36874	50	0	0
T139	0	38	0	0
T140	0	24	0	0
T158	0	10	0	0
T161	0	2	0	0
T172	0	39	0	0
T178	0	49	0	0
T195	0	62	0	0
T196	0	3	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2601	0	0
T127	0	197	0	0
T137	36874	30	0	0
T139	0	40	0	0
T140	0	22	0	0
T158	0	24	0	0
T172	0	96	0	0
T178	0	43	0	0
T195	0	75	0	0
T196	0	9	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0
T216	0	1	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2607	0	0
T127	0	205	0	0
T137	36874	21	0	0
T139	0	33	0	0
T140	0	21	0	0
T158	0	23	0	0
T161	0	8	0	0
T172	0	79	0	0
T178	0	23	0	0
T195	0	45	0	0
T196	0	6	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2707	0	0
T127	0	226	0	0
T137	36874	19	0	0
T139	0	32	0	0
T140	0	23	0	0
T158	0	1	0	0
T162	0	45	0	0
T172	0	56	0	0
T178	0	36	0	0
T195	0	100	0	0
T196	0	8	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2559	0	0
T65	29570	0	0	0
T125	6537	4	0	0
T127	0	229	0	0
T136	3365	0	0	0
T137	0	30	0	0
T139	0	24	0	0
T140	0	13	0	0
T150	3986	0	0	0
T151	5730	0	0	0
T158	0	9	0	0
T172	0	75	0	0
T178	0	29	0	0
T195	0	49	0	0
T196	0	3	0	0
T217	18088	0	0	0
T218	6535	0	0	0
T219	8278	0	0	0
T220	10424	0	0	0
T221	1522	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2651	0	0
T127	0	177	0	0
T137	36874	28	0	0
T139	0	14	0	0
T140	0	17	0	0
T158	0	9	0	0
T161	0	3	0	0
T172	0	80	0	0
T178	0	51	0	0
T195	0	49	0	0
T196	0	2	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2606	0	0
T127	0	216	0	0
T137	36874	15	0	0
T139	0	47	0	0
T140	0	39	0	0
T158	0	9	0	0
T161	0	1	0	0
T172	0	68	0	0
T178	0	21	0	0
T195	0	62	0	0
T196	0	12	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2541	0	0
T127	0	200	0	0
T137	36874	26	0	0
T139	0	25	0	0
T140	0	20	0	0
T158	0	10	0	0
T161	0	6	0	0
T172	0	84	0	0
T178	0	35	0	0
T195	0	50	0	0
T196	0	3	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2845	0	0
T127	0	192	0	0
T137	36874	28	0	0
T139	0	49	0	0
T140	0	34	0	0
T158	0	7	0	0
T161	0	3	0	0
T172	0	70	0	0
T178	0	40	0	0
T195	0	62	0	0
T196	0	12	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2762	0	0
T127	0	223	0	0
T137	36874	34	0	0
T139	0	23	0	0
T140	0	34	0	0
T158	0	4	0	0
T172	0	86	0	0
T178	0	37	0	0
T195	0	55	0	0
T196	0	9	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0
T222	0	2	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	3004	0	0
T127	0	247	0	0
T137	36874	18	0	0
T139	0	60	0	0
T140	0	28	0	0
T158	0	31	0	0
T162	0	44	0	0
T172	0	78	0	0
T178	0	69	0	0
T195	0	75	0	0
T196	0	5	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2716	0	0
T127	0	222	0	0
T137	36874	24	0	0
T139	0	48	0	0
T140	0	8	0	0
T158	0	13	0	0
T161	0	7	0	0
T172	0	86	0	0
T178	0	27	0	0
T195	0	44	0	0
T196	0	5	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2693	0	0
T127	0	230	0	0
T137	36874	17	0	0
T139	0	11	0	0
T140	0	26	0	0
T158	0	7	0	0
T161	0	5	0	0
T172	0	83	0	0
T178	0	49	0	0
T195	0	64	0	0
T196	0	10	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2458	0	0
T127	0	207	0	0
T137	36874	10	0	0
T139	0	22	0	0
T140	0	23	0	0
T158	0	23	0	0
T161	0	6	0	0
T172	0	81	0	0
T178	0	49	0	0
T195	0	48	0	0
T196	0	3	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2788	0	0
T127	0	217	0	0
T137	36874	41	0	0
T139	0	38	0	0
T140	0	19	0	0
T158	0	29	0	0
T161	0	4	0	0
T172	0	86	0	0
T178	0	36	0	0
T195	0	64	0	0
T196	0	14	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2690	0	0
T127	0	222	0	0
T137	36874	17	0	0
T139	0	23	0	0
T140	0	25	0	0
T158	0	40	0	0
T161	0	1	0	0
T172	0	73	0	0
T178	0	74	0	0
T195	0	49	0	0
T196	0	15	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22945202	2883	0	0
T127	0	205	0	0
T137	36874	19	0	0
T139	0	39	0	0
T140	0	29	0	0
T158	0	31	0	0
T161	0	2	0	0
T172	0	104	0	0
T178	0	57	0	0
T195	0	36	0	0
T196	0	8	0	0
T197	20988	0	0	0
T198	20116	0	0	0
T199	5867	0	0	0
T200	1751	0	0	0
T201	17607	0	0	0
T202	4890	0	0	0
T203	2450	0	0	0
T204	195759	0	0	0
T205	16472	0	0	0