Unified Coverage Report :: Module :: keymgr_ctrl

Module : keymgr_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.80	100.00	98.11		100.00	100.00	90.91

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl	97.80	100.00	98.11		100.00	100.00	90.91

---

Module Instance : tb.dut.u_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.80	100.00	98.11		100.00	100.00	90.91

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.99	99.71	95.29	94.16	100.00	98.65	94.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec	93.15			93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec	93.15			93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec	93.15			93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec	97.95			97.95
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec	93.15			93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec	93.15			93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec	93.15			93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec	93.15			93.15
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec	93.15			93.15
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec	93.15			93.15
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec	95.89			95.89
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec	95.89			95.89
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec	95.89			95.89
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec	93.15			93.15
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec	93.15			93.15
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec	95.89			95.89
u_cnt	100.00			100.00
u_data_en	84.15	97.44	33.33		100.00	90.00	100.00
u_err	94.81	100.00	84.44			100.00
u_hw_sel	100.00	100.00				100.00	100.00
u_key_valid_sync	100.00	100.00				100.00
u_op_state	100.00	100.00	100.00		100.00	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_ctrl

	Line No.	Total	Covered	Percent
TOTAL		194	194	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
ALWAYS	248	3	3	100.00
CONT_ASSIGN	255	1	1	100.00
ALWAYS	261	3	3	100.00
ALWAYS	264	3	3	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
ALWAYS	290	7	7	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
ALWAYS	349	21	21	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
ALWAYS	455	79	79	100.00
ALWAYS	681	4	4	100.00
ALWAYS	689	12	12	100.00
ALWAYS	725	5	5	100.00
CONT_ASSIGN	763	1	1	100.00
CONT_ASSIGN	769	1	1	100.00
CONT_ASSIGN	800	1	1	100.00
ALWAYS	808	3	3	100.00
CONT_ASSIGN	818	1	1	100.00
ROUTINE	865	1	1	100.00
ALWAYS	907	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
150	1	1
151	1	1
152	1	1
153	1	1
155	1	1
165	1	1
166	1	1
169	1	1
185	1	1
186	1	1
187	1	1
188	1	1
202	1	1
207	1	1
213	1	1
215	1	1
230	1	1
243	1	1
248	1	1
249	1	1
251	1	1
255	1	1
261	3	3
264	1	1
265	1	1
267	1	1
275	1	1
277	1	1
281	2	2
288	1	1
290	1	1
291	1	1
292	1	1
294	1	1
295	1	1
296	1	1
297	1	1
316	16	16
323	1	1
346	1	1
349	1	1
350	1	1
351	1	1
355	1	1
357	1	1
358	1	1
361	1	1
367	1	1
368	1	1
369	1	1
370	1	1
371	1	1
373		unreachable
375		unreachable
380	1	1
381	1	1
382	1	1
388	1	1
389	1	1
393	1	1
394	1	1
395	1	1
396	1	1
433	1	1
444	1	1
445	1	1
451	1	1
455	1	1
458	1	1
459	1	1
460	1	1
463	1	1
466	1	1
469	1	1
472	1	1
475	1	1
478	1	1
481	1	1
484	1	1
487	1	1
491	1	1
493	1	1
496	1	1
500	1	1
504	1	1
507	1	1
508	1	1
509	1	1
510	1	1
			MISSING_ELSE
516	1	1
517	1	1
519	1	1
520	1	1
			MISSING_ELSE
526	1	1
527	1	1
532	1	1
533		unreachable
534		unreachable
			MISSING_ELSE
540	1	1
541	1	1
542	1	1
549	1	1
552	1	1
553	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
560	1	1
561	1	1
			MISSING_ELSE
567	1	1
572	1	1
575	1	1
576	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
			MISSING_ELSE
587	1	1
592	1	1
595	1	1
596	1	1
597	1	1
598	1	1
599	1	1
600	1	1
601	1	1
			MISSING_ELSE
608	1	1
613	1	1
615	1	1
616	1	1
617	1	1
618	1	1
619	1	1
			MISSING_ELSE
628	1	1
630	1	1
631	1	1
640	1	1
641	1	1
642	1	1
			MISSING_ELSE
653	1	1
654	1	1
656	1	1
657	1	1
			MISSING_ELSE
662	1	1
663	1	1
681	1	1
682	1	1
683	1	1
684	1	1
			MISSING_ELSE
689	1	1
690	1	1
692	1	1
694	1	1
697	1	1
700	1	1
703	1	1
706	1	1
709	1	1
712	1	1
713	1	1
717	1	1
725	1	1
726	1	1
730	1	1
731	1	1
732	1	1
			MISSING_ELSE
763	1	1
769	1	1
800	1	1
808	1	1
809	1	1
811	1	1
818	1	1
865	1	1
907	3	3

---

Cond Coverage for Module : keymgr_ctrl

	Total	Covered	Percent
Conditions	212	208	98.11
Logical	212	208	98.11
Non-Logical	0	0
Event	0	0

 LINE       150
 EXPRESSION (op_i == OpAdvance)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (op_i == OpGenId)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (op_i == OpGenSwOut)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T17

 LINE       153
 EXPRESSION (op_i == OpGenHwOut)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (gen_id_op | gen_sw_op | gen_hw_op)
             ----1----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	1	0	Covered	T2,T4,T17
1	0	0	Covered	T1,T2,T3

 LINE       165
 EXPRESSION (op_start_i & adv_op & en_i)
             -----1----   ---2--   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T48,T49,T50
1	1	1	Covered	T1,T2,T4

 LINE       166
 EXPRESSION (op_start_i & gen_hw_op & en_i)
             -----1----   ----2----   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T1,T2,T4

 LINE       169
 EXPRESSION ((op_start_i & dis_op) | ((!en_i)))
             ----------1----------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T28,T51,T52

 LINE       169
 SUB-EXPRESSION (op_start_i & dis_op)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T28,T19,T51
1	0	Covered	T1,T2,T4
1	1	Covered	T28,T51,T52

 LINE       185
 EXPRESSION (op_req & adv_op)
             ---1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       186
 EXPRESSION (op_req & dis_op)
             ---1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T28,T19,T51
1	0	Covered	T1,T2,T4
1	1	Covered	T28,T51,T52

 LINE       187
 EXPRESSION (op_req & gen_id_op)
             ---1--   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       188
 EXPRESSION (op_req & (gen_sw_op | gen_hw_op))
             ---1--   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       188
 SUB-EXPRESSION (gen_sw_op | gen_hw_op)
                 ----1----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T17

 LINE       202
 EXPRESSION (adv_req & op_ack & ( ~ (op_err | op_fault_err) ))
             ---1---   ---2--   --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T15
1	1	1	Covered	T1,T2,T4

 LINE       202
 SUB-EXPRESSION (op_err | op_fault_err)
                 ---1--   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T40,T37
1	0	Covered	T1,T2,T4

 LINE       230
 EXPRESSION (wipe_req ? KeyUpdateWipe : (random_req ? KeyUpdateRandom : (init_o ? KeyUpdateRoot : op_update_sel)))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T18

 LINE       230
 SUB-EXPRESSION (random_req ? KeyUpdateRandom : (init_o ? KeyUpdateRoot : op_update_sel))
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       230
 SUB-EXPRESSION (init_o ? KeyUpdateRoot : op_update_sel)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       243
 EXPRESSION (prng_en_dis_inv_set ? 2'b11 : (prng_reseed_done_i ? ({1'b0, prng_en_dis_inv_q[1]}) : prng_en_dis_inv_q))
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T15

 LINE       243
 SUB-EXPRESSION (prng_reseed_done_i ? ({1'b0, prng_en_dis_inv_q[1]}) : prng_en_dis_inv_q)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       255
 EXPRESSION (random_req | wipe_req | prng_en_dis_inv_q[0])
             -----1----   ----2---   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T15
0	1	0	Covered	T2,T17,T18
1	0	0	Covered	T1,T2,T4

 LINE       277
 EXPRESSION (advance_sel ? cdi_cnt : op_cdi_sel_i)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       281
 EXPRESSION (invalid_stage_sel_o ? ({EntropyRounds {entropy_i[0]}}) : key_state_q[cdi_sel_o][0])
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       281
 EXPRESSION (invalid_stage_sel_o ? ({EntropyRounds {entropy_i[1]}}) : key_state_q[cdi_sel_o][1])
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       333
 EXPRESSION (root_key_i.creator_root_key_share0_valid && root_key_i.creator_root_key_share1_valid)
             --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       346
 EXPRESSION (op_req ? cnt[0] : '0)
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       389
 EXPRESSION ((adv_op || dis_op) ? kmac_data_i : key_state_q[cdi_sel_o])
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       389
 SUB-EXPRESSION (adv_op || dis_op)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T28,T51,T52
1	0	Covered	T1,T2,T4

 LINE       408
 EXPRESSION (op_ack | random_ack)
             ---1--   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       408
 EXPRESSION (op_update | random_req)
             ----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       433
 EXPRESSION (op_req ? op_ack : (init_o | invalid_op))
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       433
 SUB-EXPRESSION (init_o | invalid_op)
                 ---1--   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       444
 EXPRESSION (op_ack & adv_req & ((~op_err)))
             ---1--   ---2---   -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T15
1	1	1	Covered	T1,T2,T4

 LINE       445
 EXPRESSION (op_ack & dis_req)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T28,T51,T52
1	0	Covered	T1,T2,T4
1	1	Covered	T28,T51,T52

 LINE       504
 EXPRESSION (op_start_i & ((~advance_sel)))
             -----1----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       532
 EXPRESSION (int'(cnt) == (EntropyRounds - 1))
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Unreachable	T1,T2,T4

 LINE       542
 EXPRESSION ((en_i && root_key_valid_q) ? StCtrlInit : StCtrlWipe)
             -------------1------------

-1-	Status	Tests
0	Covered	T18,T53,T54
1	Covered	T1,T2,T4

 LINE       542
 SUB-EXPRESSION (en_i && root_key_valid_q)
                 --1-    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T55,T56
1	0	Covered	T18,T53,T54
1	1	Covered	T1,T2,T4

 LINE       552
 EXPRESSION (advance_sel ? Creator : Disable)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       553
 EXPRESSION (op_start_i & ( ~ (advance_sel | disable_sel) ))
             -----1----   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       553
 SUB-EXPRESSION (advance_sel | disable_sel)
                 -----1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T57,T51,T58
1	0	Covered	T1,T2,T4

 LINE       555
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T17,T40,T19
1	0	Covered	T57,T51,T58

 LINE       572
 EXPRESSION (disable_sel ? Disable : (advance_sel ? OwnerInt : Creator))
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T59,T51,T60

 LINE       572
 SUB-EXPRESSION (advance_sel ? OwnerInt : Creator)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       575
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T61,T62,T63
1	0	Covered	T59,T64,T65

 LINE       592
 EXPRESSION (disable_sel ? Disable : (advance_sel ? Owner : OwnerInt))
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T28,T52,T66

 LINE       592
 SUB-EXPRESSION (advance_sel ? Owner : OwnerInt)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T15

 LINE       595
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T2,T67,T44
1	0	Covered	T66,T68,T69

 LINE       613
 EXPRESSION ((disable_sel | advance_sel) ? Disable : Owner)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T5
1	Covered	T1,T15,T5

 LINE       613
 SUB-EXPRESSION (disable_sel | advance_sel)
                 -----1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T5
0	1	Covered	T1,T15,T5
1	0	Covered	T28,T70,T6

 LINE       615
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T5
0	1	Covered	T37,T71,T72
1	0	Covered	T70,T6,T73

 LINE       617
 EXPRESSION (adv_state || dis_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T5
0	1	Covered	T28,T74,T64
1	0	Covered	T1,T15,T5

 LINE       656
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T5
0	1	Covered	T20,T29,T41
1	0	Covered	T51,T75,T7

 LINE       730
 EXPRESSION (((|{error_o, fault_o})) ? OpDoneFail : OpDoneSuccess)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       763
 EXPRESSION ((adv_en_o & ( ~ (advance_sel | disable_sel) )) | (gen_en_o & ((~gen_op))))
             -----------------------1----------------------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T19,T29,T34
1	0	Covered	T21,T33,T76

 LINE       763
 SUB-EXPRESSION (adv_en_o & ( ~ (advance_sel | disable_sel) ))
                 ----1---   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T20,T21,T33

 LINE       763
 SUB-EXPRESSION (advance_sel | disable_sel)
                 -----1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       763
 SUB-EXPRESSION (gen_en_o & ((~gen_op)))
                 ----1---   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T19,T20,T29

 LINE       769
 EXPRESSION 
 Number  Term
      1  ((op_ack | op_update) & invalid) ? KeyUpdateKmac : (((op_ack | op_update) & op_fault_err) ? KeyUpdateWipe : (((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T12,T13

 LINE       769
 SUB-EXPRESSION ((op_ack | op_update) & invalid)
                 ----------1---------   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T18
1	0	Covered	T1,T2,T4
1	1	Covered	T11,T12,T13

 LINE       769
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       769
 SUB-EXPRESSION 
 Number  Term
      1  ((op_ack | op_update) & op_fault_err) ? KeyUpdateWipe : (((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T37

 LINE       769
 SUB-EXPRESSION ((op_ack | op_update) & op_fault_err)
                 ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T40,T37
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T17,T37

 LINE       769
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       769
 SUB-EXPRESSION 
 Number  Term
      1  ((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T15,T5

 LINE       769
 SUB-EXPRESSION ((op_ack | op_update) & disabled)
                 ----------1---------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T15,T5

 LINE       769
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       769
 SUB-EXPRESSION (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle))
                 ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       769
 SUB-EXPRESSION ((op_ack | op_update) & op_err)
                 ----------1---------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       769
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       769
 SUB-EXPRESSION ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       769
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       800
 EXPRESSION ((state_d != state_q) & (state_d inside {StCtrlRootKey, StCtrlCreatorRootKey, StCtrlOwnerIntKey, StCtrlOwnerKey}))
             ----------1---------   --------------------------------------------2--------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       800
 SUB-EXPRESSION (state_d != state_q)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       818
 EXPRESSION (vld_state_change_q & ((!adv_op)))
             ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Not Covered

 LINE       820
 EXPRESSION (disabled | (initialized & ((~en_i))))
             ----1---   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T57,T59,T70
1	0	Covered	T1,T15,T5

 LINE       820
 SUB-EXPRESSION (initialized & ((~en_i)))
                 -----1-----   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T57,T59,T70

 LINE       820
 EXPRESSION (state_intg_err_q | state_intg_err_d)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Not Covered

---

FSM Coverage for Module : keymgr_ctrl

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	19	19	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrlCreatorRootKey	561	Covered	T1,T2,T4
StCtrlDisabled	558	Covered	T1,T15,T5
StCtrlEntropyReseed	510	Covered	T1,T2,T4
StCtrlInit	542	Covered	T1,T2,T4
StCtrlInvalid	641	Covered	T2,T17,T18
StCtrlOwnerIntKey	581	Covered	T1,T2,T4
StCtrlOwnerKey	601	Covered	T1,T15,T5
StCtrlRandom	520	Covered	T1,T2,T4
StCtrlReset	495	Covered	T1,T2,T3
StCtrlRootKey	534	Covered	T1,T2,T4
StCtrlWipe	508	Covered	T2,T17,T18

transitions	Line No.	Covered	Tests
StCtrlCreatorRootKey->StCtrlDisabled	578	Covered	T51,T60,T77
StCtrlCreatorRootKey->StCtrlOwnerIntKey	581	Covered	T1,T2,T4
StCtrlCreatorRootKey->StCtrlWipe	576	Covered	T59,T61,T62
StCtrlDisabled->StCtrlWipe	657	Covered	T51,T75,T7
StCtrlEntropyReseed->StCtrlRandom	520	Covered	T1,T2,T4
StCtrlInit->StCtrlCreatorRootKey	561	Covered	T1,T2,T4
StCtrlInit->StCtrlDisabled	558	Covered	T68,T78,T79
StCtrlInit->StCtrlWipe	556	Covered	T17,T40,T57
StCtrlOwnerIntKey->StCtrlDisabled	598	Covered	T28,T52,T65
StCtrlOwnerIntKey->StCtrlOwnerKey	601	Covered	T1,T15,T5
StCtrlOwnerIntKey->StCtrlWipe	596	Covered	T2,T67,T44
StCtrlOwnerKey->StCtrlDisabled	618	Covered	T1,T15,T5
StCtrlOwnerKey->StCtrlWipe	616	Covered	T37,T70,T6
StCtrlRandom->StCtrlRootKey	534	Covered	T1,T2,T4
StCtrlReset->StCtrlEntropyReseed	510	Covered	T1,T2,T4
StCtrlReset->StCtrlWipe	508	Covered	T11,T12,T80
StCtrlRootKey->StCtrlInit	542	Covered	T1,T2,T4
StCtrlRootKey->StCtrlWipe	542	Covered	T18,T53,T54
StCtrlWipe->StCtrlInvalid	641	Covered	T2,T17,T18

---

Branch Coverage for Module : keymgr_ctrl

	Line No.	Total	Covered	Percent
Branches		97	97	100.00
TERNARY	230	4	4	100.00
TERNARY	243	3	3	100.00
TERNARY	277	2	2	100.00
TERNARY	346	2	2	100.00
TERNARY	433	2	2	100.00
TERNARY	769	6	6	100.00
TERNARY	281	2	2	100.00
TERNARY	281	2	2	100.00
IF	248	2	2	100.00
IF	261	2	2	100.00
IF	264	2	2	100.00
IF	290	2	2	100.00
CASE	355	7	7	100.00
CASE	493	39	39	100.00
IF	681	3	3	100.00
CASE	692	9	9	100.00
IF	726	4	4	100.00
IF	808	2	2	100.00
IF	907	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	230	(wipe_req) ? 
-2-:	230	(random_req) ? 
-3-:	230	(init_o) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T17,T18
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	243	(prng_en_dis_inv_set) ? 
-2-:	243	(prng_reseed_done_i) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T15
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	277	(advance_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	346	(op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	433	(op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	769	(((op_ack | op_update) & invalid)) ? 
-2-:	769	(((op_ack | op_update) & op_fault_err)) ? 
-3-:	769	(((op_ack | op_update) & disabled)) ? 
-4-:	769	(((op_ack | op_update) & op_err)) ? 
-5-:	769	((op_ack | op_update)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T11,T12,T13
0	1	-	-	-	Covered	T2,T17,T37
0	0	1	-	-	Covered	T1,T15,T5
0	0	0	1	-	Covered	T1,T2,T4
0	0	0	0	1	Covered	T1,T2,T4
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	281	(invalid_stage_sel_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	281	(invalid_stage_sel_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	248	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	261	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	264	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	290	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	case (update_sel)
-2-:	367	if (root_key_valid_q)
-3-:	389	((adv_op || dis_op)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
KeyUpdateRandom	-	-	Covered	T1,T2,T4
KeyUpdateRoot	1	-	Covered	T1,T2,T4
KeyUpdateRoot	0	-	Covered	T18,T53,T54
KeyUpdateKmac	-	1	Covered	T1,T2,T4
KeyUpdateKmac	-	0	Covered	T1,T2,T4
KeyUpdateWipe	-	-	Covered	T2,T17,T18
default	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	493	case (state_q)
-2-:	507	if (inv_state)
-3-:	509	if (advance_sel)
-4-:	519	if (prng_reseed_ack_i)
-5-:	532	if ((int'(cnt) == (EntropyRounds - 1)))
-6-:	542	((en_i && root_key_valid_q)) ? 
-7-:	552	(advance_sel) ? 
-8-:	555	if (((!en_i) || inv_state))
-9-:	557	if (dis_state)
-10-:	560	if (adv_state)
-11-:	572	(disable_sel) ? 
-12-:	572	(advance_sel) ? 
-13-:	575	if (((!en_i) || inv_state))
-14-:	577	if (dis_state)
-15-:	580	if (adv_state)
-16-:	592	(disable_sel) ? 
-17-:	592	(advance_sel) ? 
-18-:	595	if (((!en_i) || inv_state))
-19-:	597	if (dis_state)
-20-:	600	if (adv_state)
-21-:	613	((disable_sel | advance_sel)) ? 
-22-:	615	if (((!en_i) || inv_state))
-23-:	617	if ((adv_state || dis_state))
-24-:	640	if ((!op_start_i))
-25-:	656	if (((!en_i) || inv_state))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	Status	Tests
StCtrlReset	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T80
StCtrlReset	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StCtrlReset	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlEntropyReseed	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StCtrlEntropyReseed	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StCtrlRandom	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable	T1,T2,T4
StCtrlRandom	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StCtrlRootKey	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StCtrlRootKey	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T53,T54
StCtrlInit	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StCtrlInit	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StCtrlInit	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T40,T57
StCtrlInit	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T68,T78,T79
StCtrlInit	-	-	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StCtrlInit	-	-	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T59,T51,T60
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T59,T61,T62
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T51,T60,T77
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T28,T52,T66
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T15
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T2,T67,T44
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T28,T52,T65
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T1,T15,T5
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T1,T2,T4
StCtrlOwnerKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T15,T5
StCtrlOwnerKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T15,T5
StCtrlOwnerKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T37,T70,T6
StCtrlOwnerKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T15,T5
StCtrlOwnerKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T15,T5
StCtrlWipe	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T17,T18
StCtrlWipe	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T59,T6,T58
StCtrlDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T51,T75,T7
StCtrlDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T15,T5
StCtrlInvalid	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T17,T18
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	681	if ((!rst_ni))
-2-:	683	if (update_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T17,T18

	LineNo.	Expression
-1-:	692	case (state_q)

Branches:

-1-	Status	Tests
StCtrlReset StCtrlEntropyReseed StCtrlRandom	Covered	T1,T2,T3
StCtrlRootKey StCtrlInit	Covered	T1,T2,T4
StCtrlCreatorRootKey	Covered	T1,T2,T4
StCtrlOwnerIntKey	Covered	T1,T2,T4
StCtrlOwnerKey	Covered	T1,T15,T5
StCtrlDisabled	Covered	T1,T15,T5
StCtrlWipe	Covered	T2,T17,T18
StCtrlInvalid	Covered	T2,T17,T18
default	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	726	if (op_done_o)
-2-:	730	((|{error_o, fault_o})) ? 
-3-:	731	if (op_start_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T4
1	0	-	Covered	T1,T2,T4
0	-	1	Covered	T1,T2,T4
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	907	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	10	90.91
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	10	90.91

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntZero_A	20804434	27940	0	0
DataEnDis_A	20677398	27403	0	0
DataEn_A	20677397	5508484	0	0
GeneralLegalCommands_A	21223472	25992	0	0
InitLegalCommands_A	21223472	1071617	0	0
LoadKey_A	21190324	15377786	0	0
OwnerLegalCommands_A	21223472	1250568	0	0
SameErrCnt_A	870	870	0	0
SecCmCFILinear_A	21223472	0	0	4768
StageDisableSel_A	21223472	693428	0	0
u_state_regs_A	21223472	21067684	0	0

CntZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20804434	27940	0	0
T1	5545	20	0	0
T2	4277	19	0	0
T3	1384	0	0	0
T4	78207	22	0	0
T5	181486	27	0	0
T14	1275	0	0	0
T15	104768	22	0	0
T16	1153	0	0	0
T17	2604	25	0	0
T18	8250	32	0	0
T36	0	26	0	0
T37	0	24	0	0
T40	0	1	0	0

DataEnDis_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20677398	27403	0	0
T1	5545	20	0	0
T2	4277	19	0	0
T3	1384	0	0	0
T4	56878	18	0	0
T5	181486	27	0	0
T14	1275	0	0	0
T15	104768	22	0	0
T16	1153	0	0	0
T17	2604	25	0	0
T18	8250	32	0	0
T36	0	21	0	0
T37	0	24	0	0
T38	0	23	0	0

DataEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20677397	5508484	0	0
T1	5545	112	0	0
T2	4277	477	0	0
T3	1384	0	0	0
T4	56878	25280	0	0
T5	181486	67828	0	0
T14	1275	0	0	0
T15	104768	30649	0	0
T16	1153	0	0	0
T17	2604	0	0	0
T18	8250	0	0	0
T36	0	882	0	0
T37	0	1689	0	0
T38	0	4036	0	0
T39	0	49288	0	0
T57	0	52	0	0

GeneralLegalCommands_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21223472	25992	0	0
T6	7924	0	0	0
T28	257038	893	0	0
T52	0	4918	0	0
T70	9479	0	0	0
T81	0	284	0	0
T82	0	137	0	0
T83	0	641	0	0
T84	0	345	0	0
T85	0	1308	0	0
T86	0	11547	0	0
T87	0	2592	0	0
T88	0	1092	0	0
T89	5108	0	0	0
T90	2859	0	0	0
T91	3870	0	0	0
T92	130373	0	0	0
T93	36564	0	0	0
T94	8938	0	0	0
T95	6833	0	0	0

InitLegalCommands_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21223472	1071617	0	0
T1	5545	16	0	0
T2	4277	26	0	0
T3	1384	0	0	0
T4	78207	1694	0	0
T5	181486	8722	0	0
T14	1275	0	0	0
T15	104768	4143	0	0
T16	1153	0	0	0
T17	2604	0	0	0
T18	8250	0	0	0
T36	0	168	0	0
T37	0	284	0	0
T38	0	558	0	0
T39	0	6747	0	0
T57	0	62	0	0

LoadKey_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21190324	15377786	0	0
T1	5545	422	0	0
T2	4277	863	0	0
T3	1384	0	0	0
T4	78207	71108	0	0
T5	181486	174625	0	0
T14	1275	0	0	0
T15	104768	99852	0	0
T16	1153	0	0	0
T17	2604	151	0	0
T18	8250	0	0	0
T36	0	1749	0	0
T37	0	3602	0	0
T38	0	13516	0	0
T39	0	178230	0	0

OwnerLegalCommands_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21223472	1250568	0	0
T1	5545	42	0	0
T2	4277	0	0	0
T3	1384	0	0	0
T4	78207	0	0	0
T5	181486	12731	0	0
T14	1275	0	0	0
T15	104768	10344	0	0
T16	1153	0	0	0
T17	2604	0	0	0
T18	8250	0	0	0
T37	0	447	0	0
T38	0	1252	0	0
T39	0	19769	0	0
T46	0	42	0	0
T47	0	106	0	0
T96	0	42	0	0
T97	0	572	0	0

SameErrCnt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	870	870	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

SecCmCFILinear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21223472	0	0	4768

StageDisableSel_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21223472	693428	0	0
T1	5545	29	0	0
T2	4277	255	0	0
T3	1384	680	0	0
T4	78207	55	0	0
T5	181486	19	0	0
T14	1275	91	0	0
T15	104768	257	0	0
T16	1153	49	0	0
T17	2604	305	0	0
T18	8250	112	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21223472	21067684	0	0
T1	5545	5494	0	0
T2	4277	4080	0	0
T3	1384	1315	0	0
T4	78207	78138	0	0
T5	181486	181419	0	0
T14	1275	1187	0	0
T15	104768	104673	0	0
T16	1153	1066	0	0
T17	2604	2455	0	0
T18	8250	8193	0	0