Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3079065	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

615540

1

T1

5519

T2

387

T3

5173

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3279016	1			T1	8368		T2	771		T3	8688
values[0x0]	206841	1			T1	1865		T2	158		T3	1812
values[0x1]	208748	1			T1	1881		T2	163		T3	1814

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2112620	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1581985

1

T1

7135

T2

594

T3

6962

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16308	1			T1	56		T3	46		T14	5
valid_sources[0x01]	13070	1			T1	57		T2	3		T3	62
valid_sources[0x02]	15799	1			T1	52		T3	47		T14	2
valid_sources[0x03]	11724	1			T1	55		T2	2		T3	51
valid_sources[0x04]	11850	1			T1	58		T3	48		T14	3
valid_sources[0x05]	13764	1			T1	40		T2	16		T3	57
valid_sources[0x06]	12414	1			T1	32		T2	8		T3	32
valid_sources[0x07]	13713	1			T1	52		T2	9		T3	37
valid_sources[0x08]	12763	1			T1	58		T3	31		T14	2
valid_sources[0x09]	21827	1			T1	47		T2	10		T3	40
valid_sources[0x0a]	12216	1			T1	49		T3	36		T14	7
valid_sources[0x0b]	21068	1			T1	24		T3	55		T14	7
valid_sources[0x0c]	11977	1			T1	38		T3	50		T14	1
valid_sources[0x0d]	13485	1			T1	47		T2	11		T3	65
valid_sources[0x0e]	12024	1			T1	46		T2	2		T3	34
valid_sources[0x0f]	12972	1			T1	50		T2	11		T3	43
valid_sources[0x10]	11782	1			T1	66		T2	1		T3	47
valid_sources[0x11]	14726	1			T1	46		T2	5		T3	52
valid_sources[0x12]	11698	1			T1	35		T2	8		T3	50
valid_sources[0x13]	13288	1			T1	62		T2	3		T3	43
valid_sources[0x14]	12118	1			T1	50		T2	6		T3	46
valid_sources[0x15]	16029	1			T1	41		T3	43		T14	1
valid_sources[0x16]	11812	1			T1	44		T2	5		T3	46
valid_sources[0x17]	13140	1			T1	52		T3	48		T14	1
valid_sources[0x18]	61727	1			T1	52		T2	9		T3	50
valid_sources[0x19]	12270	1			T1	34		T2	3		T3	38
valid_sources[0x1a]	12349	1			T1	24		T3	55		T14	4
valid_sources[0x1b]	11449	1			T1	65		T2	10		T3	49
valid_sources[0x1c]	12270	1			T1	46		T3	46		T14	1
valid_sources[0x1d]	12810	1			T1	25		T2	6		T3	50
valid_sources[0x1e]	12142	1			T1	47		T2	1		T3	44
valid_sources[0x1f]	14921	1			T1	41		T2	9		T3	44
valid_sources[0x20]	12371	1			T1	54		T2	5		T3	45
valid_sources[0x21]	11839	1			T1	41		T3	57		T15	26
valid_sources[0x22]	12577	1			T1	44		T2	2		T3	51
valid_sources[0x23]	11970	1			T1	47		T2	1		T3	58
valid_sources[0x24]	12838	1			T1	59		T2	1		T3	44
valid_sources[0x25]	11350	1			T1	60		T2	1		T3	66
valid_sources[0x26]	11951	1			T1	34		T3	47		T14	3
valid_sources[0x27]	12812	1			T1	50		T2	7		T3	46
valid_sources[0x28]	11471	1			T1	53		T2	2		T3	51
valid_sources[0x29]	11742	1			T1	51		T2	1		T3	61
valid_sources[0x2a]	12280	1			T1	49		T2	7		T3	47
valid_sources[0x2b]	19671	1			T1	35		T2	4		T3	45
valid_sources[0x2c]	12052	1			T1	43		T2	8		T3	55
valid_sources[0x2d]	14761	1			T1	52		T2	1		T3	36
valid_sources[0x2e]	12420	1			T1	35		T2	7		T3	48
valid_sources[0x2f]	19819	1			T1	43		T3	59		T14	2
valid_sources[0x30]	19249	1			T1	46		T2	4		T3	44
valid_sources[0x31]	19255	1			T1	59		T3	49		T14	2
valid_sources[0x32]	12817	1			T1	49		T2	3		T3	45
valid_sources[0x33]	14207	1			T1	37		T2	5		T3	60
valid_sources[0x34]	12313	1			T1	26		T2	3		T3	51
valid_sources[0x35]	12500	1			T1	59		T3	39		T14	6
valid_sources[0x36]	11807	1			T1	46		T2	1		T3	55
valid_sources[0x37]	11880	1			T1	45		T3	49		T14	1
valid_sources[0x38]	13703	1			T1	42		T2	13		T3	43
valid_sources[0x39]	13184	1			T1	51		T2	1		T3	44
valid_sources[0x3a]	13145	1			T1	53		T2	3		T3	41
valid_sources[0x3b]	12436	1			T1	53		T2	4		T3	50
valid_sources[0x3c]	11683	1			T1	58		T2	12		T3	54
valid_sources[0x3d]	12383	1			T1	36		T2	6		T3	50
valid_sources[0x3e]	12769	1			T1	53		T2	11		T3	50
valid_sources[0x3f]	13358	1			T1	41		T2	1		T3	50
valid_sources[0x40]	15040	1			T1	39		T2	2		T3	36
valid_sources[0x41]	11540	1			T1	59		T3	50		T14	1
valid_sources[0x42]	14563	1			T1	38		T2	11		T3	56
valid_sources[0x43]	12050	1			T1	45		T3	39		T15	30
valid_sources[0x44]	13496	1			T1	51		T2	1		T3	46
valid_sources[0x45]	12317	1			T1	43		T2	9		T3	45
valid_sources[0x46]	13195	1			T1	46		T3	37		T14	9
valid_sources[0x47]	14207	1			T1	38		T3	34		T14	3
valid_sources[0x48]	19450	1			T1	64		T3	42		T15	25
valid_sources[0x49]	13841	1			T1	50		T2	2		T3	36
valid_sources[0x4a]	11949	1			T1	76		T2	2		T3	47
valid_sources[0x4b]	12630	1			T1	49		T2	10		T3	44
valid_sources[0x4c]	18489	1			T1	41		T2	8		T3	58
valid_sources[0x4d]	12490	1			T1	45		T2	1		T3	49
valid_sources[0x4e]	13647	1			T1	40		T2	11		T3	41
valid_sources[0x4f]	11758	1			T1	38		T3	42		T14	10
valid_sources[0x50]	13745	1			T1	41		T2	7		T3	39
valid_sources[0x51]	22317	1			T1	50		T3	65		T14	3
valid_sources[0x52]	12040	1			T1	58		T3	50		T14	1
valid_sources[0x53]	11558	1			T1	32		T2	3		T3	64
valid_sources[0x54]	12196	1			T1	35		T2	8		T3	25
valid_sources[0x55]	11611	1			T1	39		T2	2		T3	38
valid_sources[0x56]	12212	1			T1	46		T3	39		T14	2
valid_sources[0x57]	11804	1			T1	42		T2	1		T3	34
valid_sources[0x58]	14521	1			T1	41		T3	49		T14	5
valid_sources[0x59]	11925	1			T1	54		T3	53		T15	43
valid_sources[0x5a]	12754	1			T1	31		T2	3		T3	36
valid_sources[0x5b]	18611	1			T1	45		T2	2		T3	62
valid_sources[0x5c]	12604	1			T1	55		T2	7		T3	31
valid_sources[0x5d]	13036	1			T1	57		T3	59		T14	5
valid_sources[0x5e]	17087	1			T1	55		T2	1		T3	39
valid_sources[0x5f]	12053	1			T1	43		T2	14		T3	48
valid_sources[0x60]	18805	1			T1	51		T3	55		T14	2
valid_sources[0x61]	11357	1			T1	63		T2	2		T3	62
valid_sources[0x62]	16886	1			T1	41		T3	47		T15	14
valid_sources[0x63]	11666	1			T1	42		T3	50		T14	1
valid_sources[0x64]	11551	1			T1	40		T2	1		T3	44
valid_sources[0x65]	11744	1			T1	28		T3	34		T14	1
valid_sources[0x66]	12212	1			T1	42		T2	4		T3	53
valid_sources[0x67]	11568	1			T1	48		T2	6		T3	42
valid_sources[0x68]	12598	1			T1	48		T2	10		T3	51
valid_sources[0x69]	13269	1			T1	46		T2	7		T3	41
valid_sources[0x6a]	13145	1			T1	59		T3	57		T14	4
valid_sources[0x6b]	14265	1			T1	54		T3	44		T14	1
valid_sources[0x6c]	32483	1			T1	63		T3	47		T13	1034
valid_sources[0x6d]	12336	1			T1	48		T2	11		T3	37
valid_sources[0x6e]	12560	1			T1	44		T2	13		T3	33
valid_sources[0x6f]	12127	1			T1	34		T2	5		T3	58
valid_sources[0x70]	17689	1			T1	34		T3	50		T14	6
valid_sources[0x71]	11646	1			T1	46		T3	44		T14	2
valid_sources[0x72]	11966	1			T1	45		T3	43		T14	7
valid_sources[0x73]	14108	1			T1	60		T2	7		T3	46
valid_sources[0x74]	12139	1			T1	53		T2	4		T3	49
valid_sources[0x75]	12118	1			T1	35		T3	54		T14	1
valid_sources[0x76]	12403	1			T1	48		T2	5		T3	58
valid_sources[0x77]	19983	1			T1	66		T2	7		T3	42
valid_sources[0x78]	24559	1			T1	45		T2	1		T3	61
valid_sources[0x79]	13145	1			T1	54		T2	3		T3	43
valid_sources[0x7a]	11668	1			T1	55		T2	7		T3	53
valid_sources[0x7b]	14034	1			T1	58		T2	4		T3	36
valid_sources[0x7c]	21374	1			T1	47		T2	1		T3	39
valid_sources[0x7d]	13478	1			T1	49		T2	8		T3	60
valid_sources[0x7e]	12572	1			T1	56		T3	38		T14	5
valid_sources[0x7f]	12181	1			T1	64		T2	14		T3	46
valid_sources[0x80]	27148	1			T1	43		T3	47		T14	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

333645

1

T1

3004

T2

166

T3

2976

values[0x0]

all_enables

biggest_size

148744

1

T1

1303

T2

120

T3

1220

values[0x1]

all_enables

biggest_size

133151

1

T1

1212

T2

101

T3

977