Module Definition
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Module : keymgr_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.keymgr_csr_assert 100.00 100.00



Module Instance : tb.dut.keymgr_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : keymgr_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 32 32 100.00 32 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 32 32 100.00 32 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 23606169 14604 0 0
attest_sw_binding_0_rd_A 23606169 4014 0 0
attest_sw_binding_1_rd_A 23606169 4382 0 0
attest_sw_binding_2_rd_A 23606169 4216 0 0
attest_sw_binding_3_rd_A 23606169 4132 0 0
attest_sw_binding_4_rd_A 23606169 4220 0 0
attest_sw_binding_5_rd_A 23606169 4247 0 0
attest_sw_binding_6_rd_A 23606169 4156 0 0
attest_sw_binding_7_rd_A 23606169 4102 0 0
intr_enable_rd_A 23606169 4825 0 0
key_version_rd_A 23606169 4305 0 0
max_creator_key_ver_regwen_rd_A 23606169 4172 0 0
max_owner_int_key_ver_regwen_rd_A 23606169 4256 0 0
max_owner_key_ver_regwen_rd_A 23606169 4322 0 0
reseed_interval_regwen_rd_A 23606169 4397 0 0
salt_0_rd_A 23606169 4307 0 0
salt_1_rd_A 23606169 4215 0 0
salt_2_rd_A 23606169 4016 0 0
salt_3_rd_A 23606169 4247 0 0
salt_4_rd_A 23606169 4192 0 0
salt_5_rd_A 23606169 4171 0 0
salt_6_rd_A 23606169 4143 0 0
salt_7_rd_A 23606169 4281 0 0
sealing_sw_binding_0_rd_A 23606169 4345 0 0
sealing_sw_binding_1_rd_A 23606169 4385 0 0
sealing_sw_binding_2_rd_A 23606169 4095 0 0
sealing_sw_binding_3_rd_A 23606169 4208 0 0
sealing_sw_binding_4_rd_A 23606169 4250 0 0
sealing_sw_binding_5_rd_A 23606169 4196 0 0
sealing_sw_binding_6_rd_A 23606169 4291 0 0
sealing_sw_binding_7_rd_A 23606169 4282 0 0
sideload_clear_rd_A 23606169 4196 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 14604 0 0
T17 45094 147 0 0
T18 12220 0 0 0
T19 3547 0 0 0
T47 0 214 0 0
T64 0 1 0 0
T79 70884 0 0 0
T93 968 0 0 0
T104 4406 0 0 0
T105 0 50 0 0
T109 0 331 0 0
T119 0 317 0 0
T120 0 94 0 0
T121 0 382 0 0
T122 0 103 0 0
T123 8858 0 0 0
T124 13624 0 0 0
T125 1864 0 0 0
T126 7204 0 0 0
T127 0 40 0 0

attest_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4014 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 56 0 0
T82 3756 0 0 0
T105 20586 10 0 0
T120 0 21 0 0
T122 0 20 0 0
T127 0 21 0 0
T177 0 23 0 0
T178 0 34 0 0
T179 0 60 0 0
T180 0 32 0 0
T181 0 42 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

attest_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4382 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 60 0 0
T82 3756 0 0 0
T105 20586 33 0 0
T120 0 34 0 0
T122 0 17 0 0
T127 0 11 0 0
T177 0 9 0 0
T178 0 49 0 0
T179 0 78 0 0
T180 0 33 0 0
T181 0 38 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

attest_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4216 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 52 0 0
T82 3756 0 0 0
T105 20586 29 0 0
T120 0 30 0 0
T122 0 32 0 0
T127 0 9 0 0
T177 0 18 0 0
T178 0 33 0 0
T179 0 74 0 0
T180 0 28 0 0
T181 0 63 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

attest_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4132 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 40 0 0
T82 3756 0 0 0
T105 20586 38 0 0
T120 0 26 0 0
T122 0 34 0 0
T127 0 6 0 0
T177 0 9 0 0
T178 0 35 0 0
T179 0 73 0 0
T180 0 30 0 0
T181 0 41 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

attest_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4220 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 38 0 0
T82 3756 0 0 0
T105 20586 36 0 0
T120 0 23 0 0
T122 0 21 0 0
T127 0 7 0 0
T177 0 17 0 0
T178 0 36 0 0
T179 0 57 0 0
T180 0 20 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0
T187 0 4 0 0

attest_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4247 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 50 0 0
T82 3756 0 0 0
T105 20586 35 0 0
T120 0 44 0 0
T122 0 21 0 0
T127 0 18 0 0
T177 0 12 0 0
T178 0 26 0 0
T179 0 29 0 0
T180 0 23 0 0
T181 0 57 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

attest_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4156 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 50 0 0
T82 3756 0 0 0
T105 20586 29 0 0
T120 0 39 0 0
T122 0 31 0 0
T127 0 5 0 0
T177 0 14 0 0
T178 0 35 0 0
T179 0 58 0 0
T180 0 41 0 0
T181 0 49 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

attest_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4102 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 77 0 0
T82 3756 0 0 0
T105 20586 48 0 0
T120 0 24 0 0
T122 0 44 0 0
T127 0 17 0 0
T177 0 15 0 0
T178 0 53 0 0
T179 0 53 0 0
T180 0 9 0 0
T181 0 50 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4825 0 0
T3 151217 27 0 0
T5 0 70 0 0
T13 12740 0 0 0
T14 6736 0 0 0
T15 85790 0 0 0
T16 11895 0 0 0
T17 45094 0 0 0
T18 12220 0 0 0
T19 3547 0 0 0
T52 0 42 0 0
T54 0 9 0 0
T79 70884 0 0 0
T105 0 38 0 0
T120 0 34 0 0
T122 0 52 0 0
T123 8858 0 0 0
T127 0 32 0 0
T177 0 19 0 0
T188 0 16 0 0

key_version_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4305 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 60 0 0
T82 3756 0 0 0
T105 20586 27 0 0
T120 0 25 0 0
T122 0 36 0 0
T127 0 16 0 0
T177 0 8 0 0
T178 0 14 0 0
T179 0 59 0 0
T180 0 36 0 0
T181 0 68 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

max_creator_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4172 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 51 0 0
T82 3756 0 0 0
T105 20586 29 0 0
T120 0 33 0 0
T122 0 33 0 0
T127 0 10 0 0
T177 0 10 0 0
T178 0 33 0 0
T179 0 73 0 0
T180 0 25 0 0
T181 0 52 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

max_owner_int_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4256 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 88 0 0
T82 3756 0 0 0
T105 20586 18 0 0
T120 0 56 0 0
T122 0 26 0 0
T127 0 16 0 0
T177 0 16 0 0
T178 0 30 0 0
T179 0 34 0 0
T180 0 5 0 0
T181 0 68 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

max_owner_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4322 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 71 0 0
T82 3756 0 0 0
T105 20586 42 0 0
T120 0 37 0 0
T122 0 43 0 0
T127 0 1 0 0
T177 0 13 0 0
T178 0 51 0 0
T179 0 73 0 0
T180 0 46 0 0
T181 0 37 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

reseed_interval_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4397 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 104 0 0
T82 3756 0 0 0
T105 20586 36 0 0
T120 0 35 0 0
T122 0 39 0 0
T127 0 12 0 0
T177 0 15 0 0
T178 0 16 0 0
T179 0 53 0 0
T180 0 23 0 0
T181 0 68 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

salt_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4307 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 33 0 0
T82 3756 0 0 0
T105 20586 37 0 0
T120 0 26 0 0
T122 0 32 0 0
T127 0 38 0 0
T177 0 35 0 0
T178 0 16 0 0
T179 0 79 0 0
T180 0 21 0 0
T181 0 45 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

salt_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4215 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 85 0 0
T82 3756 0 0 0
T105 20586 16 0 0
T120 0 23 0 0
T122 0 36 0 0
T127 0 21 0 0
T177 0 19 0 0
T178 0 41 0 0
T179 0 53 0 0
T180 0 34 0 0
T181 0 67 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

salt_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4016 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 58 0 0
T82 3756 0 0 0
T105 20586 33 0 0
T120 0 22 0 0
T122 0 59 0 0
T127 0 12 0 0
T177 0 10 0 0
T178 0 20 0 0
T179 0 62 0 0
T180 0 18 0 0
T181 0 68 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

salt_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4247 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 48 0 0
T82 3756 0 0 0
T105 20586 43 0 0
T120 0 25 0 0
T122 0 33 0 0
T127 0 9 0 0
T177 0 16 0 0
T178 0 15 0 0
T179 0 57 0 0
T180 0 19 0 0
T181 0 65 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

salt_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4192 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 51 0 0
T82 3756 0 0 0
T105 20586 36 0 0
T120 0 29 0 0
T122 0 56 0 0
T127 0 6 0 0
T177 0 17 0 0
T178 0 16 0 0
T179 0 56 0 0
T180 0 14 0 0
T181 0 70 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

salt_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4171 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 61 0 0
T82 3756 0 0 0
T105 20586 36 0 0
T120 0 28 0 0
T122 0 32 0 0
T127 0 17 0 0
T177 0 4 0 0
T178 0 20 0 0
T179 0 54 0 0
T180 0 35 0 0
T181 0 31 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

salt_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4143 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 44 0 0
T82 3756 0 0 0
T105 20586 15 0 0
T120 0 34 0 0
T122 0 39 0 0
T127 0 10 0 0
T177 0 16 0 0
T178 0 24 0 0
T179 0 71 0 0
T180 0 28 0 0
T181 0 39 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

salt_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4281 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 56 0 0
T82 3756 0 0 0
T105 20586 27 0 0
T120 0 14 0 0
T122 0 35 0 0
T127 0 15 0 0
T177 0 19 0 0
T178 0 23 0 0
T179 0 59 0 0
T180 0 12 0 0
T181 0 56 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

sealing_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4345 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 58 0 0
T82 3756 0 0 0
T105 20586 37 0 0
T120 0 25 0 0
T122 0 40 0 0
T127 0 11 0 0
T177 0 17 0 0
T178 0 22 0 0
T179 0 56 0 0
T180 0 17 0 0
T181 0 49 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

sealing_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4385 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 51 0 0
T82 3756 0 0 0
T105 20586 33 0 0
T120 0 35 0 0
T122 0 34 0 0
T127 0 8 0 0
T177 0 34 0 0
T178 0 43 0 0
T179 0 54 0 0
T180 0 36 0 0
T181 0 48 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

sealing_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4095 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 50 0 0
T82 3756 0 0 0
T105 20586 11 0 0
T120 0 32 0 0
T122 0 22 0 0
T127 0 11 0 0
T177 0 33 0 0
T178 0 44 0 0
T179 0 47 0 0
T180 0 20 0 0
T181 0 36 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

sealing_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4208 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 52 0 0
T82 3756 0 0 0
T105 20586 15 0 0
T120 0 19 0 0
T122 0 35 0 0
T127 0 16 0 0
T177 0 3 0 0
T178 0 23 0 0
T179 0 54 0 0
T180 0 27 0 0
T181 0 53 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

sealing_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4250 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 40 0 0
T82 3756 0 0 0
T105 20586 25 0 0
T120 0 25 0 0
T122 0 17 0 0
T127 0 5 0 0
T177 0 6 0 0
T178 0 20 0 0
T179 0 47 0 0
T180 0 24 0 0
T181 0 57 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

sealing_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4196 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 44 0 0
T82 3756 0 0 0
T105 20586 46 0 0
T120 0 28 0 0
T122 0 25 0 0
T127 0 5 0 0
T177 0 10 0 0
T178 0 31 0 0
T179 0 51 0 0
T180 0 20 0 0
T181 0 61 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

sealing_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4291 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 39 0 0
T82 3756 0 0 0
T105 20586 25 0 0
T120 0 30 0 0
T122 0 40 0 0
T127 0 9 0 0
T177 0 17 0 0
T178 0 21 0 0
T179 0 47 0 0
T180 0 19 0 0
T181 0 61 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

sealing_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4282 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 91 0 0
T82 3756 0 0 0
T105 20586 34 0 0
T120 0 45 0 0
T122 0 23 0 0
T127 0 11 0 0
T177 0 10 0 0
T178 0 58 0 0
T179 0 35 0 0
T180 0 21 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0
T189 0 3 0 0

sideload_clear_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23606169 4196 0 0
T22 11433 0 0 0
T41 3643 0 0 0
T51 13864 0 0 0
T78 0 58 0 0
T82 3756 0 0 0
T105 20586 28 0 0
T120 0 23 0 0
T122 0 31 0 0
T127 0 16 0 0
T177 0 14 0 0
T178 0 30 0 0
T179 0 53 0 0
T180 0 18 0 0
T181 0 71 0 0
T182 2219 0 0 0
T183 62685 0 0 0
T184 8977 0 0 0
T185 8303 0 0 0
T186 9697 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%