Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3386542	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

636674

1

T1

163

T2

458

T3

247

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3590154	1			T1	614		T2	774		T3	964
values[0x0]	214993	1			T1	40		T2	181		T3	59
values[0x1]	218069	1			T1	47		T2	176		T3	85

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2318262	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1704954

1

T1

304

T2

660

T3

498

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12526	1			T1	17		T4	1		T12	4
valid_sources[0x01]	15747	1			T1	2		T4	11		T12	1
valid_sources[0x02]	16311	1			T4	2		T12	2		T13	1
valid_sources[0x03]	14950	1			T4	9		T12	4		T13	5
valid_sources[0x04]	12695	1			T1	3		T4	4		T12	7
valid_sources[0x05]	32490	1			T1	1		T4	3		T12	3
valid_sources[0x06]	12813	1			T4	8		T12	3		T13	5
valid_sources[0x07]	13605	1			T1	4		T4	4		T12	6
valid_sources[0x08]	12241	1			T1	2		T4	3		T12	3
valid_sources[0x09]	16110	1			T4	3		T12	4		T13	5
valid_sources[0x0a]	13323	1			T4	1		T12	8		T15	16
valid_sources[0x0b]	14514	1			T1	2		T4	3		T12	2
valid_sources[0x0c]	26306	1			T1	2		T4	11		T12	9
valid_sources[0x0d]	12445	1			T1	2		T4	13		T12	8
valid_sources[0x0e]	12326	1			T12	2		T13	7		T14	2
valid_sources[0x0f]	12443	1			T4	8		T12	4		T13	2
valid_sources[0x10]	13332	1			T1	5		T12	4		T13	4
valid_sources[0x11]	13641	1			T4	2		T12	6		T13	4
valid_sources[0x12]	17821	1			T1	2		T4	4		T12	5
valid_sources[0x13]	14404	1			T4	3		T12	5		T13	2
valid_sources[0x14]	13684	1			T1	5		T4	11		T12	3
valid_sources[0x15]	15030	1			T4	2		T12	3		T13	2
valid_sources[0x16]	13378	1			T4	4		T12	9		T15	13
valid_sources[0x17]	12323	1			T1	2		T12	3		T13	4
valid_sources[0x18]	12635	1			T1	3		T4	8		T12	1
valid_sources[0x19]	12503	1			T1	1		T4	2		T12	7
valid_sources[0x1a]	13099	1			T12	4		T13	2		T15	33
valid_sources[0x1b]	16717	1			T1	7		T4	13		T12	9
valid_sources[0x1c]	12450	1			T4	1		T12	4		T13	3
valid_sources[0x1d]	12423	1			T1	2		T4	2		T12	7
valid_sources[0x1e]	16523	1			T4	3		T12	4		T13	3
valid_sources[0x1f]	29385	1			T1	8		T4	2		T12	8
valid_sources[0x20]	14120	1			T1	7		T12	1		T13	5
valid_sources[0x21]	12791	1			T4	4		T12	6		T13	6
valid_sources[0x22]	16168	1			T1	2		T4	5		T12	4
valid_sources[0x23]	13209	1			T1	2		T4	5		T12	5
valid_sources[0x24]	16261	1			T1	10		T4	3		T12	2
valid_sources[0x25]	13411	1			T4	2		T12	8		T13	3
valid_sources[0x26]	12312	1			T12	1		T13	7		T15	15
valid_sources[0x27]	13063	1			T4	1		T12	5		T13	2
valid_sources[0x28]	12677	1			T4	4		T12	6		T13	2
valid_sources[0x29]	14500	1			T1	2		T4	6		T12	4
valid_sources[0x2a]	12901	1			T4	6		T12	8		T13	1
valid_sources[0x2b]	12244	1			T1	5		T4	5		T12	8
valid_sources[0x2c]	12992	1			T1	1		T4	5		T12	5
valid_sources[0x2d]	13746	1			T1	3		T4	4		T12	4
valid_sources[0x2e]	12045	1			T1	8		T12	3		T13	3
valid_sources[0x2f]	12890	1			T1	5		T4	4		T12	3
valid_sources[0x30]	12883	1			T1	3		T12	6		T13	4
valid_sources[0x31]	12811	1			T4	9		T12	5		T14	1
valid_sources[0x32]	16099	1			T1	11		T4	7		T12	11
valid_sources[0x33]	18053	1			T1	4		T4	4		T12	5
valid_sources[0x34]	14706	1			T1	3		T12	2		T13	1
valid_sources[0x35]	13022	1			T1	1		T4	2		T12	2
valid_sources[0x36]	13402	1			T1	1		T4	4		T12	1
valid_sources[0x37]	15433	1			T4	9		T12	9		T15	22
valid_sources[0x38]	12266	1			T1	5		T4	17		T12	5
valid_sources[0x39]	14798	1			T4	6		T12	6		T15	17
valid_sources[0x3a]	15905	1			T12	4		T13	2		T14	2
valid_sources[0x3b]	13339	1			T4	3		T13	2		T15	29
valid_sources[0x3c]	12575	1			T12	5		T13	6		T15	14
valid_sources[0x3d]	12598	1			T4	2		T12	4		T13	3
valid_sources[0x3e]	15305	1			T1	9		T4	14		T12	3
valid_sources[0x3f]	12652	1			T4	6		T12	3		T15	18
valid_sources[0x40]	13190	1			T4	4		T12	6		T13	1
valid_sources[0x41]	12964	1			T1	9		T4	5		T12	4
valid_sources[0x42]	12936	1			T1	8		T4	7		T12	5
valid_sources[0x43]	12161	1			T1	13		T4	2		T12	7
valid_sources[0x44]	12697	1			T4	3		T12	1		T13	2
valid_sources[0x45]	12030	1			T4	5		T12	4		T13	4
valid_sources[0x46]	18624	1			T1	10		T4	2		T12	4
valid_sources[0x47]	12708	1			T4	7		T12	4		T15	20
valid_sources[0x48]	15925	1			T1	2		T4	3		T12	6
valid_sources[0x49]	12770	1			T1	6		T4	2		T12	6
valid_sources[0x4a]	30730	1			T1	4		T4	3		T12	3
valid_sources[0x4b]	14827	1			T1	4		T4	3		T12	5
valid_sources[0x4c]	14811	1			T1	2		T4	4		T12	7
valid_sources[0x4d]	12257	1			T4	1		T12	4		T13	5
valid_sources[0x4e]	13772	1			T1	8		T4	9		T12	5
valid_sources[0x4f]	14037	1			T4	13		T12	5		T13	2
valid_sources[0x50]	13209	1			T1	5		T4	11		T12	1
valid_sources[0x51]	23231	1			T4	2		T12	6		T13	1
valid_sources[0x52]	13861	1			T4	15		T12	5		T13	4
valid_sources[0x53]	12954	1			T4	3		T12	2		T13	1
valid_sources[0x54]	19880	1			T1	6		T4	4		T12	2
valid_sources[0x55]	12722	1			T1	2		T4	5		T12	9
valid_sources[0x56]	14472	1			T1	2		T4	8		T12	3
valid_sources[0x57]	13457	1			T4	1		T12	6		T13	6
valid_sources[0x58]	13208	1			T1	2		T4	4		T12	8
valid_sources[0x59]	28888	1			T4	1		T12	7		T13	3
valid_sources[0x5a]	12742	1			T4	1		T12	5		T13	8
valid_sources[0x5b]	12563	1			T1	8		T4	1		T12	10
valid_sources[0x5c]	12648	1			T1	1		T4	12		T12	4
valid_sources[0x5d]	71890	1			T1	1		T4	3		T12	4
valid_sources[0x5e]	14386	1			T4	2		T12	5		T13	6
valid_sources[0x5f]	13759	1			T4	3		T12	4		T13	4
valid_sources[0x60]	12897	1			T4	8		T12	4		T13	2
valid_sources[0x61]	13832	1			T1	10		T4	16		T12	3
valid_sources[0x62]	14170	1			T4	6		T12	2		T13	2
valid_sources[0x63]	13098	1			T4	6		T12	4		T13	2
valid_sources[0x64]	13222	1			T4	4		T12	7		T15	25
valid_sources[0x65]	13864	1			T1	2		T4	2		T12	3
valid_sources[0x66]	13398	1			T4	4		T12	3		T13	5
valid_sources[0x67]	12788	1			T1	6		T4	3		T12	2
valid_sources[0x68]	13062	1			T1	4		T4	11		T12	10
valid_sources[0x69]	12448	1			T1	3		T12	4		T13	8
valid_sources[0x6a]	12030	1			T1	7		T4	7		T12	3
valid_sources[0x6b]	16329	1			T1	5		T4	5		T12	6
valid_sources[0x6c]	12950	1			T1	6		T4	8		T12	2
valid_sources[0x6d]	12008	1			T4	2		T12	5		T13	2
valid_sources[0x6e]	12511	1			T4	15		T12	4		T13	3
valid_sources[0x6f]	15050	1			T4	2		T12	5		T13	6
valid_sources[0x70]	13065	1			T1	10		T4	3		T12	3
valid_sources[0x71]	13226	1			T4	7		T12	6		T13	2
valid_sources[0x72]	13361	1			T4	1		T12	3		T13	4
valid_sources[0x73]	17119	1			T1	10		T4	5		T12	6
valid_sources[0x74]	13051	1			T1	1		T4	3		T12	4
valid_sources[0x75]	12834	1			T1	4		T4	4		T12	7
valid_sources[0x76]	14123	1			T4	8		T12	5		T13	3
valid_sources[0x77]	14122	1			T1	3		T4	1		T12	4
valid_sources[0x78]	12844	1			T1	1		T4	2		T12	2
valid_sources[0x79]	14931	1			T3	1108		T4	20		T12	4
valid_sources[0x7a]	12730	1			T1	1		T4	3		T12	6
valid_sources[0x7b]	14437	1			T1	1		T12	6		T13	4
valid_sources[0x7c]	37069	1			T1	3		T4	15		T12	5
valid_sources[0x7d]	36217	1			T4	9		T12	1		T13	2
valid_sources[0x7e]	11976	1			T4	1		T12	2		T13	3
valid_sources[0x7f]	20955	1			T4	1		T12	2		T13	3
valid_sources[0x80]	13412	1			T1	1		T4	2		T12	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

342653

1

T1

134

T2

193

T3

203

values[0x0]

all_enables

biggest_size

154649

1

T1

17

T2

138

T3

27

values[0x1]

all_enables

biggest_size

139372

1

T1

12

T2

127

T3

17