Module Definition
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Module : keymgr_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.keymgr_csr_assert 100.00 100.00


Module Instance : tb.dut.keymgr_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : keymgr_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 32 32 100.00 32 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 32 32 100.00 32 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 25052224 20364 0 0
attest_sw_binding_0_rd_A 25052224 1424 0 0
attest_sw_binding_1_rd_A 25052224 1485 0 0
attest_sw_binding_2_rd_A 25052224 1510 0 0
attest_sw_binding_3_rd_A 25052224 1312 0 0
attest_sw_binding_4_rd_A 25052224 1430 0 0
attest_sw_binding_5_rd_A 25052224 1386 0 0
attest_sw_binding_6_rd_A 25052224 1349 0 0
attest_sw_binding_7_rd_A 25052224 1390 0 0
intr_enable_rd_A 25052224 1930 0 0
key_version_rd_A 25052224 1432 0 0
max_creator_key_ver_regwen_rd_A 25052224 1458 0 0
max_owner_int_key_ver_regwen_rd_A 25052224 1517 0 0
max_owner_key_ver_regwen_rd_A 25052224 1440 0 0
reseed_interval_regwen_rd_A 25052224 1532 0 0
salt_0_rd_A 25052224 1419 0 0
salt_1_rd_A 25052224 1460 0 0
salt_2_rd_A 25052224 1400 0 0
salt_3_rd_A 25052224 1378 0 0
salt_4_rd_A 25052224 1448 0 0
salt_5_rd_A 25052224 1508 0 0
salt_6_rd_A 25052224 1361 0 0
salt_7_rd_A 25052224 1484 0 0
sealing_sw_binding_0_rd_A 25052224 1476 0 0
sealing_sw_binding_1_rd_A 25052224 1356 0 0
sealing_sw_binding_2_rd_A 25052224 1443 0 0
sealing_sw_binding_3_rd_A 25052224 1266 0 0
sealing_sw_binding_4_rd_A 25052224 1597 0 0
sealing_sw_binding_5_rd_A 25052224 1563 0 0
sealing_sw_binding_6_rd_A 25052224 1294 0 0
sealing_sw_binding_7_rd_A 25052224 1477 0 0
sideload_clear_rd_A 25052224 1327 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 20364 0 0
T8 2999 0 0 0
T21 4352 0 0 0
T73 0 1154 0 0
T81 0 281 0 0
T88 16054 630 0 0
T89 11979 0 0 0
T90 80044 0 0 0
T91 12703 0 0 0
T92 5437 0 0 0
T93 3679 0 0 0
T122 0 159 0 0
T133 0 182 0 0
T134 0 513 0 0
T136 0 15 0 0
T137 0 461 0 0
T138 0 737 0 0
T144 0 252 0 0
T145 10522 0 0 0
T146 919 0 0 0

attest_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1424 0 0
T81 0 23 0 0
T136 23347 54 0 0
T137 16096 0 0 0
T191 0 24 0 0
T192 0 80 0 0
T193 0 15 0 0
T194 0 3 0 0
T195 0 12 0 0
T196 0 12 0 0
T197 0 61 0 0
T198 0 24 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

attest_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1485 0 0
T81 0 24 0 0
T136 23347 29 0 0
T137 16096 0 0 0
T191 0 42 0 0
T192 0 35 0 0
T193 0 9 0 0
T194 0 3 0 0
T195 0 10 0 0
T196 0 18 0 0
T197 0 40 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0
T207 0 6 0 0

attest_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1510 0 0
T81 0 21 0 0
T132 0 8 0 0
T136 23347 43 0 0
T137 16096 0 0 0
T191 0 44 0 0
T192 0 61 0 0
T193 0 10 0 0
T195 0 26 0 0
T196 0 17 0 0
T197 0 53 0 0
T198 0 9 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

attest_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1312 0 0
T81 0 29 0 0
T132 0 37 0 0
T136 23347 31 0 0
T137 16096 0 0 0
T191 0 40 0 0
T192 0 33 0 0
T193 0 18 0 0
T194 0 2 0 0
T195 0 15 0 0
T196 0 16 0 0
T197 0 16 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

attest_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1430 0 0
T81 0 57 0 0
T132 0 32 0 0
T136 23347 26 0 0
T137 16096 0 0 0
T191 0 49 0 0
T192 0 50 0 0
T193 0 1 0 0
T195 0 27 0 0
T196 0 15 0 0
T197 0 20 0 0
T198 0 14 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

attest_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1386 0 0
T81 0 23 0 0
T136 23347 19 0 0
T137 16096 0 0 0
T191 0 18 0 0
T192 0 53 0 0
T193 0 7 0 0
T194 0 8 0 0
T195 0 9 0 0
T196 0 28 0 0
T197 0 7 0 0
T198 0 7 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

attest_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1349 0 0
T81 0 37 0 0
T136 23347 33 0 0
T137 16096 0 0 0
T191 0 14 0 0
T192 0 44 0 0
T193 0 18 0 0
T194 0 11 0 0
T195 0 20 0 0
T196 0 8 0 0
T197 0 2 0 0
T198 0 22 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

attest_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1390 0 0
T81 0 24 0 0
T132 0 42 0 0
T136 23347 45 0 0
T137 16096 0 0 0
T191 0 26 0 0
T192 0 69 0 0
T194 0 15 0 0
T195 0 12 0 0
T196 0 11 0 0
T197 0 42 0 0
T198 0 7 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1930 0 0
T70 0 92 0 0
T81 0 19 0 0
T82 0 18 0 0
T134 30261 0 0 0
T136 0 30 0 0
T191 0 38 0 0
T192 0 56 0 0
T193 0 1 0 0
T208 972142 21 0 0
T209 0 58 0 0
T210 0 29 0 0
T211 8334 0 0 0
T212 83880 0 0 0
T213 3577 0 0 0
T214 2351 0 0 0
T215 5741 0 0 0
T216 176240 0 0 0
T217 6052 0 0 0
T218 2044 0 0 0

key_version_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1432 0 0
T81 0 24 0 0
T136 23347 29 0 0
T137 16096 0 0 0
T191 0 28 0 0
T192 0 73 0 0
T194 0 19 0 0
T195 0 15 0 0
T196 0 21 0 0
T197 0 11 0 0
T198 0 16 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0
T219 0 1 0 0

max_creator_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1458 0 0
T81 0 25 0 0
T132 0 41 0 0
T136 23347 30 0 0
T137 16096 0 0 0
T191 0 47 0 0
T192 0 78 0 0
T194 0 16 0 0
T195 0 21 0 0
T196 0 12 0 0
T197 0 47 0 0
T198 0 17 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

max_owner_int_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1517 0 0
T81 0 23 0 0
T132 0 30 0 0
T136 23347 30 0 0
T137 16096 0 0 0
T191 0 14 0 0
T192 0 54 0 0
T193 0 1 0 0
T195 0 15 0 0
T196 0 5 0 0
T197 0 47 0 0
T198 0 32 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

max_owner_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1440 0 0
T81 0 44 0 0
T132 0 35 0 0
T136 23347 10 0 0
T137 16096 0 0 0
T191 0 25 0 0
T192 0 33 0 0
T194 0 7 0 0
T195 0 12 0 0
T196 0 24 0 0
T197 0 69 0 0
T198 0 19 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

reseed_interval_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1532 0 0
T81 0 44 0 0
T132 0 42 0 0
T136 23347 29 0 0
T137 16096 0 0 0
T191 0 18 0 0
T192 0 49 0 0
T194 0 17 0 0
T195 0 11 0 0
T196 0 28 0 0
T197 0 17 0 0
T198 0 7 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

salt_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1419 0 0
T81 0 27 0 0
T136 23347 36 0 0
T137 16096 0 0 0
T191 0 58 0 0
T192 0 47 0 0
T193 0 9 0 0
T194 0 11 0 0
T195 0 20 0 0
T196 0 12 0 0
T197 0 63 0 0
T198 0 17 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

salt_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1460 0 0
T81 0 20 0 0
T136 23347 16 0 0
T137 16096 0 0 0
T191 0 5 0 0
T192 0 52 0 0
T193 0 10 0 0
T194 0 9 0 0
T195 0 10 0 0
T196 0 18 0 0
T197 0 82 0 0
T198 0 37 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

salt_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1400 0 0
T81 0 37 0 0
T136 23347 16 0 0
T137 16096 0 0 0
T191 0 54 0 0
T192 0 55 0 0
T193 0 12 0 0
T194 0 18 0 0
T195 0 7 0 0
T196 0 14 0 0
T197 0 17 0 0
T198 0 13 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

salt_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1378 0 0
T81 0 31 0 0
T132 0 40 0 0
T136 23347 19 0 0
T137 16096 0 0 0
T191 0 18 0 0
T192 0 56 0 0
T193 0 7 0 0
T195 0 23 0 0
T196 0 35 0 0
T197 0 32 0 0
T198 0 12 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

salt_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1448 0 0
T81 0 12 0 0
T136 23347 27 0 0
T137 16096 0 0 0
T191 0 28 0 0
T192 0 43 0 0
T193 0 6 0 0
T194 0 5 0 0
T195 0 24 0 0
T196 0 11 0 0
T197 0 74 0 0
T198 0 33 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

salt_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1508 0 0
T81 0 37 0 0
T132 0 33 0 0
T136 23347 24 0 0
T137 16096 0 0 0
T191 0 24 0 0
T192 0 72 0 0
T194 0 2 0 0
T195 0 28 0 0
T196 0 13 0 0
T197 0 72 0 0
T198 0 38 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

salt_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1361 0 0
T81 0 22 0 0
T136 23347 40 0 0
T137 16096 0 0 0
T191 0 22 0 0
T192 0 47 0 0
T193 0 8 0 0
T194 0 6 0 0
T195 0 22 0 0
T196 0 16 0 0
T197 0 53 0 0
T198 0 12 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

salt_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1484 0 0
T81 0 41 0 0
T136 23347 26 0 0
T137 16096 0 0 0
T191 0 32 0 0
T192 0 23 0 0
T193 0 20 0 0
T194 0 14 0 0
T195 0 7 0 0
T196 0 16 0 0
T197 0 39 0 0
T198 0 25 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

sealing_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1476 0 0
T81 0 49 0 0
T136 23347 40 0 0
T137 16096 0 0 0
T191 0 33 0 0
T192 0 40 0 0
T193 0 19 0 0
T194 0 19 0 0
T195 0 8 0 0
T196 0 27 0 0
T197 0 34 0 0
T198 0 11 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

sealing_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1356 0 0
T81 0 29 0 0
T132 0 19 0 0
T136 23347 43 0 0
T137 16096 0 0 0
T191 0 32 0 0
T192 0 23 0 0
T193 0 20 0 0
T194 0 13 0 0
T195 0 3 0 0
T196 0 13 0 0
T197 0 41 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

sealing_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1443 0 0
T81 0 47 0 0
T136 23347 33 0 0
T137 16096 0 0 0
T191 0 22 0 0
T192 0 59 0 0
T193 0 9 0 0
T194 0 4 0 0
T195 0 12 0 0
T196 0 18 0 0
T197 0 45 0 0
T198 0 25 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

sealing_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1266 0 0
T81 0 18 0 0
T136 23347 25 0 0
T137 16096 0 0 0
T191 0 22 0 0
T192 0 51 0 0
T193 0 5 0 0
T194 0 10 0 0
T195 0 12 0 0
T196 0 16 0 0
T197 0 10 0 0
T198 0 26 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

sealing_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1597 0 0
T81 0 29 0 0
T136 23347 32 0 0
T137 16096 0 0 0
T191 0 48 0 0
T192 0 59 0 0
T193 0 12 0 0
T194 0 3 0 0
T195 0 18 0 0
T196 0 24 0 0
T197 0 63 0 0
T198 0 26 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

sealing_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1563 0 0
T81 0 25 0 0
T132 0 32 0 0
T136 23347 35 0 0
T137 16096 0 0 0
T191 0 39 0 0
T192 0 69 0 0
T194 0 5 0 0
T195 0 19 0 0
T196 0 25 0 0
T197 0 59 0 0
T198 0 24 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

sealing_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1294 0 0
T81 0 29 0 0
T136 23347 35 0 0
T137 16096 0 0 0
T191 0 49 0 0
T192 0 47 0 0
T193 0 1 0 0
T194 0 9 0 0
T195 0 14 0 0
T196 0 17 0 0
T197 0 36 0 0
T198 0 12 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

sealing_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1477 0 0
T81 0 58 0 0
T136 23347 17 0 0
T137 16096 0 0 0
T191 0 26 0 0
T192 0 35 0 0
T193 0 9 0 0
T194 0 17 0 0
T195 0 18 0 0
T196 0 10 0 0
T197 0 52 0 0
T198 0 38 0 0
T199 18976 0 0 0
T200 3679 0 0 0
T201 3690 0 0 0
T202 57409 0 0 0
T203 12807 0 0 0
T204 6821 0 0 0
T205 3347 0 0 0
T206 1584 0 0 0

sideload_clear_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25052224 1327 0 0
T27 5718 0 0 0
T36 10866 4 0 0
T50 5512 0 0 0
T57 4451 0 0 0
T75 4668 0 0 0
T81 0 25 0 0
T111 1284 0 0 0
T136 0 30 0 0
T162 6913 0 0 0
T191 0 27 0 0
T192 0 44 0 0
T194 0 11 0 0
T195 0 21 0 0
T196 0 9 0 0
T197 0 1 0 0
T198 0 4 0 0
T220 5071 0 0 0
T221 4341 0 0 0
T222 6546 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%