Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2937607	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

648223

1

T1

263

T2

43

T3

231

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3157239	1			T1	645		T2	103		T3	311
values[0x0]	212508	1			T1	83		T2	22		T3	87
values[0x1]	216083	1			T1	88		T2	28		T3	69

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2021806	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1564024

1

T1

391

T2

72

T3

281

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10862	1			T1	2		T4	2		T11	1
valid_sources[0x01]	14640	1			T1	3		T4	1		T12	2
valid_sources[0x02]	12605	1			T2	2		T4	3		T12	4
valid_sources[0x03]	11765	1			T4	7		T11	5		T12	2
valid_sources[0x04]	22354	1			T1	4		T2	2		T4	2
valid_sources[0x05]	9964	1			T4	2		T11	1		T13	5
valid_sources[0x06]	10935	1			T2	2		T4	2		T11	3
valid_sources[0x07]	10785	1			T2	2		T4	1		T12	1
valid_sources[0x08]	12782	1			T2	1		T4	2		T11	1
valid_sources[0x09]	12161	1			T1	8		T2	3		T11	1
valid_sources[0x0a]	12013	1			T1	9		T2	4		T4	4
valid_sources[0x0b]	12270	1			T4	3		T12	4		T13	8
valid_sources[0x0c]	10488	1			T4	2		T11	9		T12	3
valid_sources[0x0d]	11901	1			T1	4		T4	2		T11	2
valid_sources[0x0e]	10279	1			T4	4		T13	6		T14	27
valid_sources[0x0f]	11643	1			T1	6		T4	2		T12	1
valid_sources[0x10]	13447	1			T4	2		T11	3		T5	6
valid_sources[0x11]	9989	1			T4	5		T11	1		T12	1
valid_sources[0x12]	15374	1			T1	12		T4	10		T11	2
valid_sources[0x13]	17574	1			T1	2		T2	1		T4	7
valid_sources[0x14]	10653	1			T1	2		T4	1		T11	3
valid_sources[0x15]	11026	1			T4	4		T12	2		T13	10
valid_sources[0x16]	11698	1			T1	15		T4	1		T11	1
valid_sources[0x17]	10949	1			T2	1		T4	1		T11	3
valid_sources[0x18]	14029	1			T4	2		T11	1		T13	5
valid_sources[0x19]	14309	1			T1	2		T4	5		T11	2
valid_sources[0x1a]	12657	1			T4	1		T11	3		T5	418
valid_sources[0x1b]	10661	1			T1	9		T2	1		T4	4
valid_sources[0x1c]	10136	1			T1	23		T4	2		T11	1
valid_sources[0x1d]	13705	1			T1	3		T4	4		T11	1
valid_sources[0x1e]	15166	1			T2	1		T11	4		T13	9
valid_sources[0x1f]	45353	1			T1	2		T4	1		T11	3
valid_sources[0x20]	16017	1			T4	1		T12	1		T13	8
valid_sources[0x21]	11416	1			T1	2		T4	2		T11	3
valid_sources[0x22]	11305	1			T2	1		T4	2		T13	9
valid_sources[0x23]	59359	1			T1	1		T2	1		T11	4
valid_sources[0x24]	11297	1			T1	7		T4	3		T12	1
valid_sources[0x25]	10896	1			T1	3		T2	1		T4	5
valid_sources[0x26]	14302	1			T1	20		T4	4		T11	2
valid_sources[0x27]	13088	1			T12	3		T13	6		T14	1
valid_sources[0x28]	18088	1			T4	5		T11	2		T13	8
valid_sources[0x29]	10466	1			T1	10		T4	1		T11	2
valid_sources[0x2a]	11931	1			T4	3		T12	2		T13	2
valid_sources[0x2b]	10185	1			T1	1		T4	3		T13	7
valid_sources[0x2c]	12395	1			T4	2		T11	1		T12	1
valid_sources[0x2d]	14616	1			T4	3		T12	2		T13	12
valid_sources[0x2e]	9788	1			T4	1		T11	2		T12	1
valid_sources[0x2f]	12860	1			T1	7		T2	2		T11	2
valid_sources[0x30]	15529	1			T1	1		T2	2		T4	6
valid_sources[0x31]	11571	1			T4	7		T11	2		T13	9
valid_sources[0x32]	11883	1			T1	5		T13	10		T43	1
valid_sources[0x33]	12534	1			T2	1		T4	2		T11	1
valid_sources[0x34]	10642	1			T1	6		T2	3		T4	2
valid_sources[0x35]	9522	1			T4	2		T11	4		T13	8
valid_sources[0x36]	13678	1			T4	1		T11	1		T12	2
valid_sources[0x37]	12465	1			T13	6		T14	15		T43	2
valid_sources[0x38]	15728	1			T2	1		T4	3		T13	8
valid_sources[0x39]	13172	1			T4	2		T11	3		T12	2
valid_sources[0x3a]	12461	1			T1	12		T2	1		T4	4
valid_sources[0x3b]	10288	1			T4	4		T11	3		T12	1
valid_sources[0x3c]	10824	1			T1	4		T2	2		T5	195
valid_sources[0x3d]	11353	1			T4	2		T11	9		T13	11
valid_sources[0x3e]	11399	1			T4	5		T12	2		T13	8
valid_sources[0x3f]	10904	1			T4	1		T11	3		T13	5
valid_sources[0x40]	14341	1			T2	1		T4	1		T11	1
valid_sources[0x41]	10683	1			T4	7		T11	4		T12	1
valid_sources[0x42]	10278	1			T2	1		T4	2		T11	3
valid_sources[0x43]	123100	1			T11	5		T13	7		T44	3
valid_sources[0x44]	11381	1			T4	5		T12	2		T13	5
valid_sources[0x45]	20054	1			T2	2		T4	5		T12	1
valid_sources[0x46]	11728	1			T2	1		T4	1		T11	2
valid_sources[0x47]	12980	1			T2	1		T4	2		T11	1
valid_sources[0x48]	16275	1			T1	1		T4	2		T13	8
valid_sources[0x49]	10658	1			T2	2		T4	6		T11	2
valid_sources[0x4a]	12248	1			T4	4		T11	3		T12	1
valid_sources[0x4b]	10240	1			T1	6		T2	4		T4	6
valid_sources[0x4c]	10529	1			T4	1		T11	1		T12	1
valid_sources[0x4d]	18789	1			T4	2		T11	6		T13	5
valid_sources[0x4e]	13606	1			T2	1		T4	1		T11	2
valid_sources[0x4f]	10284	1			T4	1		T11	1		T12	2
valid_sources[0x50]	10389	1			T1	1		T4	5		T11	4
valid_sources[0x51]	11469	1			T1	22		T4	2		T12	1
valid_sources[0x52]	10805	1			T4	4		T11	1		T13	7
valid_sources[0x53]	15802	1			T2	1		T4	2		T11	2
valid_sources[0x54]	14154	1			T1	6		T2	1		T4	2
valid_sources[0x55]	11942	1			T1	17		T11	5		T12	1
valid_sources[0x56]	11509	1			T4	2		T11	1		T12	1
valid_sources[0x57]	11789	1			T2	4		T4	4		T11	1
valid_sources[0x58]	12392	1			T1	9		T11	2		T13	6
valid_sources[0x59]	12488	1			T1	10		T2	1		T4	8
valid_sources[0x5a]	11458	1			T1	3		T4	2		T11	1
valid_sources[0x5b]	11607	1			T4	8		T11	2		T12	3
valid_sources[0x5c]	10582	1			T5	514		T12	1		T13	11
valid_sources[0x5d]	10457	1			T2	1		T4	3		T11	2
valid_sources[0x5e]	14547	1			T4	4		T11	3		T13	9
valid_sources[0x5f]	12893	1			T11	3		T12	1		T13	6
valid_sources[0x60]	20235	1			T1	6		T4	2		T13	9
valid_sources[0x61]	11049	1			T1	7		T2	2		T4	3
valid_sources[0x62]	26848	1			T2	2		T4	3		T13	5
valid_sources[0x63]	10677	1			T2	3		T4	2		T12	2
valid_sources[0x64]	10250	1			T1	11		T4	3		T11	1
valid_sources[0x65]	19430	1			T1	21		T11	7		T13	10
valid_sources[0x66]	10535	1			T1	17		T4	1		T11	1
valid_sources[0x67]	12752	1			T2	1		T4	1		T12	1
valid_sources[0x68]	10632	1			T1	12		T4	3		T12	2
valid_sources[0x69]	11325	1			T4	3		T11	2		T12	2
valid_sources[0x6a]	10677	1			T4	2		T13	5		T15	1
valid_sources[0x6b]	12714	1			T1	6		T11	2		T13	10
valid_sources[0x6c]	12632	1			T2	1		T3	467		T4	6
valid_sources[0x6d]	10773	1			T1	3		T4	9		T11	2
valid_sources[0x6e]	12898	1			T4	2		T12	3		T13	4
valid_sources[0x6f]	35720	1			T2	1		T12	2		T13	7
valid_sources[0x70]	11845	1			T1	10		T2	1		T4	8
valid_sources[0x71]	10114	1			T2	1		T4	2		T11	1
valid_sources[0x72]	9732	1			T2	1		T4	2		T11	5
valid_sources[0x73]	13863	1			T2	1		T4	10		T11	1
valid_sources[0x74]	11079	1			T4	1		T11	3		T12	1
valid_sources[0x75]	11985	1			T11	2		T12	2		T13	10
valid_sources[0x76]	11439	1			T1	10		T2	1		T4	6
valid_sources[0x77]	10429	1			T4	4		T13	6		T14	12
valid_sources[0x78]	11092	1			T2	1		T4	1		T12	2
valid_sources[0x79]	27539	1			T1	1		T4	5		T11	5
valid_sources[0x7a]	11909	1			T1	25		T13	5		T43	2
valid_sources[0x7b]	11420	1			T2	1		T4	1		T11	3
valid_sources[0x7c]	13679	1			T4	1		T11	2		T13	5
valid_sources[0x7d]	10155	1			T1	5		T2	2		T4	5
valid_sources[0x7e]	9912	1			T1	8		T4	1		T11	1
valid_sources[0x7f]	12817	1			T2	1		T4	6		T11	1
valid_sources[0x80]	11387	1			T1	4		T4	9		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

358313

1

T1

208

T2

27

T3

126

values[0x0]

all_enables

biggest_size

152398

1

T1

35

T2

8

T3

58

values[0x1]

all_enables

biggest_size

137512

1

T1

20

T2

8

T3

47