Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2539522	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

607923

1

T1

412

T2

139

T3

160

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2734723	1			T1	830		T2	543		T3	15504
values[0x0]	205130	1			T1	165		T2	47		T3	43
values[0x1]	207592	1			T1	159		T2	37		T3	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1751388	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1396057

1

T1

629

T2

280

T3

5369

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10592	1			T1	5		T11	12		T12	5
valid_sources[0x01]	24236	1			T1	11		T11	9		T13	8
valid_sources[0x02]	9799	1			T1	3		T11	11		T12	4
valid_sources[0x03]	10230	1			T1	4		T11	12		T12	9
valid_sources[0x04]	9390	1			T1	7		T11	11		T12	4
valid_sources[0x05]	13902	1			T1	5		T11	14		T12	8
valid_sources[0x06]	23575	1			T1	5		T11	10		T12	6
valid_sources[0x07]	10729	1			T1	6		T11	14		T12	4
valid_sources[0x08]	13888	1			T1	3		T11	10		T13	4
valid_sources[0x09]	9238	1			T1	10		T11	12		T13	13
valid_sources[0x0a]	9592	1			T1	11		T11	18		T12	3
valid_sources[0x0b]	9679	1			T1	2		T11	5		T12	6
valid_sources[0x0c]	9073	1			T1	2		T11	10		T12	5
valid_sources[0x0d]	9313	1			T1	5		T11	9		T12	1
valid_sources[0x0e]	9217	1			T1	7		T11	9		T13	2
valid_sources[0x0f]	11447	1			T1	9		T11	4		T12	2
valid_sources[0x10]	11153	1			T1	5		T11	4		T12	4
valid_sources[0x11]	9311	1			T1	4		T11	10		T13	3
valid_sources[0x12]	9636	1			T1	3		T11	4		T12	3
valid_sources[0x13]	9294	1			T1	6		T11	5		T12	3
valid_sources[0x14]	9838	1			T1	5		T11	12		T12	5
valid_sources[0x15]	9470	1			T1	5		T11	2		T12	1
valid_sources[0x16]	9591	1			T1	2		T11	8		T12	2
valid_sources[0x17]	9395	1			T1	3		T11	10		T12	1
valid_sources[0x18]	10161	1			T1	4		T11	13		T12	3
valid_sources[0x19]	9294	1			T11	3		T12	2		T13	5
valid_sources[0x1a]	9484	1			T1	1		T11	6		T12	7
valid_sources[0x1b]	9662	1			T1	1		T11	11		T12	5
valid_sources[0x1c]	11067	1			T1	4		T11	9		T12	1
valid_sources[0x1d]	9653	1			T1	3		T11	10		T12	2
valid_sources[0x1e]	10687	1			T1	8		T11	5		T12	1
valid_sources[0x1f]	10756	1			T1	2		T11	11		T13	4
valid_sources[0x20]	10434	1			T1	9		T11	4		T12	2
valid_sources[0x21]	13021	1			T1	7		T11	7		T12	3
valid_sources[0x22]	13904	1			T1	6		T11	4		T12	1
valid_sources[0x23]	10776	1			T1	1		T11	10		T13	6
valid_sources[0x24]	9070	1			T1	5		T11	7		T12	2
valid_sources[0x25]	26298	1			T1	6		T11	13		T12	5
valid_sources[0x26]	20009	1			T1	4		T11	14		T13	3
valid_sources[0x27]	11436	1			T1	6		T11	13		T12	6
valid_sources[0x28]	9462	1			T1	6		T11	11		T12	2
valid_sources[0x29]	10910	1			T1	2		T11	9		T12	4
valid_sources[0x2a]	14886	1			T1	5		T11	6		T13	4
valid_sources[0x2b]	10032	1			T1	7		T11	10		T12	2
valid_sources[0x2c]	12286	1			T1	7		T11	5		T12	3
valid_sources[0x2d]	9786	1			T1	5		T11	8		T12	1
valid_sources[0x2e]	9788	1			T1	4		T11	11		T12	3
valid_sources[0x2f]	10843	1			T1	4		T11	11		T12	1
valid_sources[0x30]	9262	1			T1	4		T11	9		T12	6
valid_sources[0x31]	9413	1			T1	2		T11	2		T12	4
valid_sources[0x32]	12563	1			T1	6		T11	4		T12	4
valid_sources[0x33]	12310	1			T1	4		T11	8		T12	2
valid_sources[0x34]	10520	1			T1	2		T11	3		T12	1
valid_sources[0x35]	11609	1			T1	2		T11	9		T12	2
valid_sources[0x36]	13149	1			T1	11		T11	12		T12	3
valid_sources[0x37]	9973	1			T1	4		T11	6		T12	2
valid_sources[0x38]	10107	1			T1	2		T11	10		T12	2
valid_sources[0x39]	15717	1			T1	6		T11	6		T13	5
valid_sources[0x3a]	12109	1			T1	6		T11	8		T12	2
valid_sources[0x3b]	9345	1			T1	6		T11	10		T12	2
valid_sources[0x3c]	10263	1			T1	2		T11	9		T12	3
valid_sources[0x3d]	9944	1			T1	6		T11	6		T12	2
valid_sources[0x3e]	11396	1			T1	5		T11	10		T12	4
valid_sources[0x3f]	9552	1			T1	4		T11	11		T13	6
valid_sources[0x40]	10137	1			T11	13		T12	1		T13	12
valid_sources[0x41]	10687	1			T1	3		T11	7		T12	1
valid_sources[0x42]	9292	1			T1	3		T11	10		T12	5
valid_sources[0x43]	10586	1			T1	2		T11	9		T12	5
valid_sources[0x44]	9964	1			T1	5		T11	31		T12	1
valid_sources[0x45]	9811	1			T1	1		T11	2		T12	3
valid_sources[0x46]	71361	1			T1	5		T11	6		T12	2
valid_sources[0x47]	12008	1			T1	10		T11	10		T12	5
valid_sources[0x48]	10959	1			T1	7		T11	2		T13	4
valid_sources[0x49]	14186	1			T11	11		T12	3		T13	1
valid_sources[0x4a]	10400	1			T1	6		T11	8		T13	2
valid_sources[0x4b]	9705	1			T1	6		T11	4		T12	1
valid_sources[0x4c]	9946	1			T1	6		T11	12		T12	2
valid_sources[0x4d]	14454	1			T1	5		T11	2		T12	3
valid_sources[0x4e]	13132	1			T1	5		T11	9		T12	2
valid_sources[0x4f]	10527	1			T1	4		T11	10		T12	1
valid_sources[0x50]	10125	1			T1	8		T11	9		T12	2
valid_sources[0x51]	40163	1			T1	1		T11	5		T12	4
valid_sources[0x52]	10814	1			T1	2		T11	5		T12	4
valid_sources[0x53]	9164	1			T1	9		T11	5		T12	3
valid_sources[0x54]	12793	1			T1	9		T11	2		T12	2
valid_sources[0x55]	9692	1			T1	10		T11	6		T12	1
valid_sources[0x56]	10942	1			T1	6		T2	627		T11	4
valid_sources[0x57]	9701	1			T1	7		T11	11		T12	2
valid_sources[0x58]	10366	1			T1	3		T11	1		T12	1
valid_sources[0x59]	11164	1			T1	10		T11	10		T12	1
valid_sources[0x5a]	9000	1			T1	4		T11	6		T13	10
valid_sources[0x5b]	25280	1			T1	4		T3	15586		T12	5
valid_sources[0x5c]	10422	1			T1	2		T11	8		T12	4
valid_sources[0x5d]	14422	1			T1	2		T11	11		T12	3
valid_sources[0x5e]	9500	1			T1	8		T11	10		T12	2
valid_sources[0x5f]	9506	1			T1	5		T11	4		T12	6
valid_sources[0x60]	11080	1			T1	9		T11	4		T12	1
valid_sources[0x61]	9787	1			T1	4		T11	3		T12	3
valid_sources[0x62]	11068	1			T1	2		T11	5		T12	4
valid_sources[0x63]	13589	1			T1	10		T11	7		T12	5
valid_sources[0x64]	9373	1			T1	2		T11	4		T12	4
valid_sources[0x65]	9288	1			T1	3		T11	14		T12	6
valid_sources[0x66]	22490	1			T1	4		T11	4		T12	5
valid_sources[0x67]	9146	1			T11	3		T12	1		T13	6
valid_sources[0x68]	11982	1			T1	4		T11	6		T12	3
valid_sources[0x69]	11009	1			T1	3		T11	7		T12	1
valid_sources[0x6a]	9906	1			T1	5		T11	7		T13	3
valid_sources[0x6b]	11265	1			T1	3		T11	6		T12	3
valid_sources[0x6c]	13608	1			T1	6		T11	5		T12	1
valid_sources[0x6d]	10082	1			T1	2		T11	6		T12	3
valid_sources[0x6e]	9594	1			T1	3		T11	7		T12	6
valid_sources[0x6f]	12141	1			T1	3		T11	8		T12	3
valid_sources[0x70]	10037	1			T1	5		T11	9		T12	1
valid_sources[0x71]	18913	1			T1	8		T11	6		T12	2
valid_sources[0x72]	10952	1			T1	2		T11	4		T12	1
valid_sources[0x73]	11116	1			T1	3		T11	5		T12	2
valid_sources[0x74]	8989	1			T1	3		T11	18		T12	1
valid_sources[0x75]	17366	1			T1	4		T11	6		T12	2
valid_sources[0x76]	17461	1			T1	1		T11	11		T12	2
valid_sources[0x77]	12715	1			T1	2		T11	15		T12	6
valid_sources[0x78]	22224	1			T1	8		T11	4		T13	10
valid_sources[0x79]	14074	1			T1	7		T11	12		T12	3
valid_sources[0x7a]	11086	1			T1	5		T11	7		T13	3
valid_sources[0x7b]	9192	1			T1	8		T11	14		T12	3
valid_sources[0x7c]	10562	1			T1	6		T11	10		T12	1
valid_sources[0x7d]	10539	1			T1	3		T11	11		T12	2
valid_sources[0x7e]	10342	1			T1	6		T11	9		T12	1
valid_sources[0x7f]	12810	1			T1	6		T11	13		T12	2
valid_sources[0x80]	17623	1			T1	2		T11	9		T13	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

326963

1

T1

186

T2

113

T3

138

values[0x0]

all_enables

biggest_size

148079

1

T1

123

T2

19

T3

16

values[0x1]

all_enables

biggest_size

132881

1

T1

103

T2

7

T3

6