Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
17796672 |
17637678 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17796672 |
17637678 |
0 |
0 |
T1 |
4452 |
4373 |
0 |
0 |
T2 |
5527 |
5451 |
0 |
0 |
T3 |
68665 |
68597 |
0 |
0 |
T11 |
5693 |
5616 |
0 |
0 |
T12 |
2326 |
2228 |
0 |
0 |
T13 |
4186 |
4109 |
0 |
0 |
T14 |
3443 |
3373 |
0 |
0 |
T15 |
5352 |
5226 |
0 |
0 |
T16 |
17145 |
17008 |
0 |
0 |
T17 |
4680 |
4614 |
0 |
0 |