Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	19569645	17390	0	0
attest_sw_binding_0_rd_A	19569645	2938	0	0
attest_sw_binding_1_rd_A	19569645	3006	0	0
attest_sw_binding_2_rd_A	19569645	2972	0	0
attest_sw_binding_3_rd_A	19569645	2928	0	0
attest_sw_binding_4_rd_A	19569645	2941	0	0
attest_sw_binding_5_rd_A	19569645	3057	0	0
attest_sw_binding_6_rd_A	19569645	2964	0	0
attest_sw_binding_7_rd_A	19569645	2854	0	0
intr_enable_rd_A	19569645	3385	0	0
key_version_rd_A	19569645	3036	0	0
max_creator_key_ver_regwen_rd_A	19569645	3068	0	0
max_owner_int_key_ver_regwen_rd_A	19569645	2972	0	0
max_owner_key_ver_regwen_rd_A	19569645	2813	0	0
reseed_interval_regwen_rd_A	19569645	3076	0	0
salt_0_rd_A	19569645	2804	0	0
salt_1_rd_A	19569645	2995	0	0
salt_2_rd_A	19569645	2913	0	0
salt_3_rd_A	19569645	2834	0	0
salt_4_rd_A	19569645	2911	0	0
salt_5_rd_A	19569645	3199	0	0
salt_6_rd_A	19569645	3040	0	0
salt_7_rd_A	19569645	2884	0	0
sealing_sw_binding_0_rd_A	19569645	2884	0	0
sealing_sw_binding_1_rd_A	19569645	2949	0	0
sealing_sw_binding_2_rd_A	19569645	2782	0	0
sealing_sw_binding_3_rd_A	19569645	2891	0	0
sealing_sw_binding_4_rd_A	19569645	2848	0	0
sealing_sw_binding_5_rd_A	19569645	2891	0	0
sealing_sw_binding_6_rd_A	19569645	2919	0	0
sealing_sw_binding_7_rd_A	19569645	3095	0	0
sideload_clear_rd_A	19569645	2916	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	17390	0	0
T59	0	145	0	0
T73	0	863	0	0
T99	6560	0	0	0
T118	12501	566	0	0
T127	0	291	0	0
T129	0	303	0	0
T130	0	1299	0	0
T131	0	339	0	0
T133	0	48	0	0
T134	19730	0	0	0
T135	10535	0	0	0
T136	3788	0	0	0
T137	4215	0	0	0
T138	2862	0	0	0
T139	62045	0	0	0
T140	5785	0	0	0
T141	8284	0	0	0
T142	0	262	0	0
T148	0	980	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2938	0	0
T37	14804	0	0	0
T59	46305	44	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	16	0	0
T133	0	37	0	0
T186	0	51	0	0
T187	0	16	0	0
T188	0	23	0	0
T189	0	11	0	0
T190	0	25	0	0
T191	0	15	0	0
T192	0	10	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	3006	0	0
T37	14804	0	0	0
T59	46305	62	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	20	0	0
T133	0	33	0	0
T186	0	43	0	0
T187	0	12	0	0
T188	0	12	0	0
T189	0	48	0	0
T190	0	46	0	0
T191	0	13	0	0
T192	0	1	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2972	0	0
T37	14804	0	0	0
T59	46305	37	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	25	0	0
T133	0	36	0	0
T186	0	35	0	0
T187	0	24	0	0
T188	0	16	0	0
T189	0	43	0	0
T190	0	37	0	0
T191	0	9	0	0
T192	0	33	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2928	0	0
T37	14804	0	0	0
T59	46305	45	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	26	0	0
T133	0	32	0	0
T186	0	47	0	0
T187	0	11	0	0
T188	0	38	0	0
T189	0	36	0	0
T190	0	43	0	0
T191	0	1	0	0
T192	0	8	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2941	0	0
T37	14804	0	0	0
T59	46305	46	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	17	0	0
T133	0	27	0	0
T186	0	46	0	0
T187	0	10	0	0
T188	0	17	0	0
T189	0	43	0	0
T190	0	28	0	0
T191	0	9	0	0
T192	0	3	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	3057	0	0
T37	14804	0	0	0
T59	46305	14	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	12	0	0
T133	0	28	0	0
T186	0	68	0	0
T187	0	11	0	0
T188	0	21	0	0
T189	0	27	0	0
T190	0	29	0	0
T191	0	19	0	0
T192	0	6	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2964	0	0
T37	14804	0	0	0
T59	46305	18	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	37	0	0
T133	0	35	0	0
T186	0	38	0	0
T187	0	14	0	0
T188	0	21	0	0
T189	0	53	0	0
T190	0	47	0	0
T191	0	18	0	0
T192	0	25	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2854	0	0
T37	14804	0	0	0
T59	46305	38	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	30	0	0
T133	0	28	0	0
T186	0	60	0	0
T187	0	16	0	0
T188	0	34	0	0
T189	0	16	0	0
T190	0	18	0	0
T192	0	17	0	0
T193	0	31	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	3385	0	0
T6	0	20	0	0
T37	14804	0	0	0
T52	0	36	0	0
T59	46305	39	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T112	0	28	0	0
T129	0	58	0	0
T133	0	49	0	0
T186	0	49	0	0
T187	0	17	0	0
T188	0	26	0	0
T194	0	24	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	3036	0	0
T37	14804	0	0	0
T59	46305	33	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	27	0	0
T133	0	31	0	0
T186	0	52	0	0
T187	0	4	0	0
T188	0	35	0	0
T189	0	32	0	0
T190	0	37	0	0
T191	0	19	0	0
T192	0	25	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	3068	0	0
T37	14804	0	0	0
T59	46305	30	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	34	0	0
T133	0	32	0	0
T186	0	55	0	0
T187	0	22	0	0
T188	0	21	0	0
T189	0	18	0	0
T190	0	24	0	0
T191	0	22	0	0
T192	0	16	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2972	0	0
T37	14804	0	0	0
T59	46305	19	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	28	0	0
T133	0	20	0	0
T186	0	55	0	0
T187	0	26	0	0
T188	0	24	0	0
T189	0	12	0	0
T190	0	42	0	0
T191	0	20	0	0
T192	0	2	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2813	0	0
T37	14804	0	0	0
T59	46305	39	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	16	0	0
T133	0	18	0	0
T186	0	57	0	0
T187	0	1	0	0
T188	0	20	0	0
T189	0	25	0	0
T190	0	44	0	0
T191	0	14	0	0
T192	0	15	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	3076	0	0
T37	14804	0	0	0
T59	46305	42	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	27	0	0
T133	0	23	0	0
T186	0	38	0	0
T187	0	13	0	0
T188	0	17	0	0
T189	0	39	0	0
T190	0	28	0	0
T191	0	8	0	0
T192	0	6	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2804	0	0
T37	14804	0	0	0
T59	46305	46	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	37	0	0
T133	0	15	0	0
T186	0	48	0	0
T187	0	12	0	0
T188	0	26	0	0
T189	0	22	0	0
T190	0	34	0	0
T191	0	6	0	0
T192	0	9	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2995	0	0
T37	14804	0	0	0
T59	46305	34	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	28	0	0
T133	0	26	0	0
T186	0	84	0	0
T187	0	8	0	0
T188	0	34	0	0
T189	0	18	0	0
T190	0	32	0	0
T191	0	14	0	0
T192	0	19	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2913	0	0
T37	14804	0	0	0
T59	46305	30	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	26	0	0
T133	0	18	0	0
T186	0	55	0	0
T187	0	22	0	0
T188	0	12	0	0
T189	0	19	0	0
T190	0	36	0	0
T191	0	19	0	0
T192	0	13	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2834	0	0
T37	14804	0	0	0
T59	46305	26	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	25	0	0
T133	0	21	0	0
T186	0	53	0	0
T187	0	28	0	0
T188	0	13	0	0
T189	0	48	0	0
T190	0	35	0	0
T191	0	26	0	0
T192	0	9	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2911	0	0
T37	14804	0	0	0
T59	46305	22	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	35	0	0
T133	0	18	0	0
T186	0	42	0	0
T187	0	20	0	0
T188	0	44	0	0
T189	0	46	0	0
T190	0	41	0	0
T191	0	31	0	0
T192	0	2	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	3199	0	0
T37	14804	0	0	0
T59	46305	53	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	23	0	0
T133	0	56	0	0
T186	0	49	0	0
T187	0	21	0	0
T188	0	17	0	0
T189	0	28	0	0
T190	0	30	0	0
T191	0	17	0	0
T192	0	4	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	3040	0	0
T37	14804	0	0	0
T59	46305	51	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	30	0	0
T133	0	36	0	0
T186	0	63	0	0
T187	0	6	0	0
T188	0	15	0	0
T189	0	25	0	0
T190	0	56	0	0
T191	0	24	0	0
T192	0	10	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2884	0	0
T37	14804	0	0	0
T59	46305	16	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	33	0	0
T133	0	28	0	0
T186	0	61	0	0
T187	0	15	0	0
T188	0	25	0	0
T189	0	31	0	0
T190	0	39	0	0
T191	0	12	0	0
T192	0	13	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2884	0	0
T37	14804	0	0	0
T59	46305	9	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	36	0	0
T133	0	21	0	0
T186	0	47	0	0
T187	0	23	0	0
T188	0	45	0	0
T189	0	49	0	0
T190	0	34	0	0
T191	0	10	0	0
T192	0	23	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2949	0	0
T37	14804	0	0	0
T59	46305	42	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	28	0	0
T133	0	34	0	0
T186	0	47	0	0
T187	0	4	0	0
T188	0	44	0	0
T189	0	36	0	0
T190	0	35	0	0
T192	0	11	0	0
T193	0	33	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2782	0	0
T37	14804	0	0	0
T59	46305	30	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	26	0	0
T133	0	44	0	0
T186	0	40	0	0
T187	0	16	0	0
T188	0	19	0	0
T189	0	19	0	0
T190	0	30	0	0
T191	0	2	0	0
T192	0	12	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2891	0	0
T37	14804	0	0	0
T59	46305	30	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	24	0	0
T133	0	32	0	0
T186	0	59	0	0
T187	0	23	0	0
T188	0	11	0	0
T189	0	37	0	0
T190	0	45	0	0
T191	0	15	0	0
T192	0	5	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2848	0	0
T37	14804	0	0	0
T59	46305	34	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	21	0	0
T133	0	21	0	0
T186	0	47	0	0
T187	0	9	0	0
T188	0	16	0	0
T189	0	14	0	0
T190	0	28	0	0
T191	0	26	0	0
T192	0	14	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2891	0	0
T37	14804	0	0	0
T59	46305	26	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	28	0	0
T133	0	23	0	0
T186	0	62	0	0
T187	0	22	0	0
T188	0	27	0	0
T189	0	38	0	0
T190	0	34	0	0
T191	0	7	0	0
T192	0	19	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2919	0	0
T37	14804	0	0	0
T59	46305	45	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	17	0	0
T133	0	18	0	0
T186	0	71	0	0
T187	0	18	0	0
T188	0	41	0	0
T189	0	16	0	0
T190	0	35	0	0
T191	0	1	0	0
T195	0	2	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	3095	0	0
T37	14804	0	0	0
T59	46305	48	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	28	0	0
T133	0	22	0	0
T186	0	58	0	0
T187	0	22	0	0
T188	0	51	0	0
T189	0	22	0	0
T190	0	38	0	0
T191	0	20	0	0
T192	0	33	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19569645	2916	0	0
T37	14804	0	0	0
T59	46305	50	0	0
T70	91268	0	0	0
T82	948	0	0	0
T83	11133	0	0	0
T84	21671	0	0	0
T85	6950	0	0	0
T86	7436	0	0	0
T87	3776	0	0	0
T88	14921	0	0	0
T129	0	46	0	0
T133	0	16	0	0
T186	0	49	0	0
T187	0	23	0	0
T188	0	43	0	0
T189	0	20	0	0
T190	0	17	0	0
T191	0	5	0	0
T192	0	21	0	0