Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2997786	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

636057

1

T1

157

T2

726

T3

415

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3203799	1			T1	481		T2	1362		T3	386
values[0x0]	213018	1			T1	45		T2	111		T3	177
values[0x1]	217026	1			T1	51		T2	134		T3	186

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2057666	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1576177

1

T1

268

T2

943

T3

480

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12223	1			T1	5		T3	10		T11	16
valid_sources[0x01]	11865	1			T1	1		T2	2		T3	4
valid_sources[0x02]	89604	1			T1	1		T2	4		T11	10
valid_sources[0x03]	11358	1			T1	2		T2	11		T3	2
valid_sources[0x04]	36271	1			T2	2		T3	1		T11	8
valid_sources[0x05]	10404	1			T2	3		T11	2		T13	2
valid_sources[0x06]	11738	1			T1	1		T2	1		T11	7
valid_sources[0x07]	10371	1			T1	2		T11	8		T13	1
valid_sources[0x08]	11388	1			T2	3		T11	9		T13	6
valid_sources[0x09]	13307	1			T2	6		T11	12		T14	6
valid_sources[0x0a]	11915	1			T1	3		T2	1		T11	9
valid_sources[0x0b]	19212	1			T1	2		T2	3		T3	4
valid_sources[0x0c]	11483	1			T1	5		T3	2		T11	8
valid_sources[0x0d]	13340	1			T1	1		T2	11		T3	5
valid_sources[0x0e]	10371	1			T1	5		T2	3		T11	12
valid_sources[0x0f]	10790	1			T1	1		T2	7		T11	7
valid_sources[0x10]	10294	1			T1	2		T2	16		T3	4
valid_sources[0x11]	12560	1			T2	10		T3	17		T11	4
valid_sources[0x12]	56560	1			T1	1		T3	5		T11	9
valid_sources[0x13]	11952	1			T1	3		T2	7		T3	3
valid_sources[0x14]	10249	1			T1	2		T2	10		T3	2
valid_sources[0x15]	9962	1			T1	1		T11	7		T13	1
valid_sources[0x16]	11541	1			T1	1		T2	12		T3	5
valid_sources[0x17]	12281	1			T1	1		T2	1		T3	7
valid_sources[0x18]	11039	1			T1	1		T2	19		T3	4
valid_sources[0x19]	10714	1			T1	2		T2	10		T11	11
valid_sources[0x1a]	10682	1			T1	4		T2	2		T3	3
valid_sources[0x1b]	10207	1			T1	1		T2	6		T3	25
valid_sources[0x1c]	10449	1			T1	1		T2	3		T11	13
valid_sources[0x1d]	11961	1			T1	1		T11	6		T13	1
valid_sources[0x1e]	18354	1			T1	3		T2	3		T3	5
valid_sources[0x1f]	13457	1			T1	3		T3	2		T11	8
valid_sources[0x20]	30345	1			T1	2		T3	2		T11	11
valid_sources[0x21]	11220	1			T11	4		T13	2		T14	3
valid_sources[0x22]	12534	1			T1	3		T2	8		T3	8
valid_sources[0x23]	10629	1			T1	4		T11	4		T14	2
valid_sources[0x24]	10838	1			T1	2		T3	5		T11	8
valid_sources[0x25]	12125	1			T1	2		T2	13		T3	2
valid_sources[0x26]	10302	1			T1	1		T2	20		T11	10
valid_sources[0x27]	11281	1			T1	3		T2	10		T3	1
valid_sources[0x28]	10492	1			T2	1		T3	9		T11	12
valid_sources[0x29]	10709	1			T1	6		T2	7		T11	7
valid_sources[0x2a]	11231	1			T1	3		T2	3		T11	4
valid_sources[0x2b]	10775	1			T1	2		T2	4		T11	8
valid_sources[0x2c]	11448	1			T1	3		T2	11		T3	11
valid_sources[0x2d]	13297	1			T1	2		T2	7		T3	4
valid_sources[0x2e]	11045	1			T1	2		T2	8		T11	1
valid_sources[0x2f]	11445	1			T1	2		T3	7		T11	10
valid_sources[0x30]	28536	1			T1	3		T2	10		T11	8
valid_sources[0x31]	10686	1			T1	3		T2	2		T11	6
valid_sources[0x32]	17332	1			T2	4		T11	11		T13	5
valid_sources[0x33]	10191	1			T1	1		T2	30		T3	16
valid_sources[0x34]	10958	1			T1	1		T2	9		T11	5
valid_sources[0x35]	12441	1			T2	12		T3	3		T11	7
valid_sources[0x36]	12296	1			T1	5		T2	4		T3	1
valid_sources[0x37]	10322	1			T1	4		T2	35		T3	8
valid_sources[0x38]	10319	1			T1	2		T2	16		T3	4
valid_sources[0x39]	10801	1			T2	6		T11	13		T13	3
valid_sources[0x3a]	9924	1			T1	3		T2	9		T3	3
valid_sources[0x3b]	11439	1			T1	2		T2	4		T11	12
valid_sources[0x3c]	19060	1			T1	2		T2	7		T3	2
valid_sources[0x3d]	25458	1			T1	1		T2	5		T3	7
valid_sources[0x3e]	12922	1			T1	4		T3	1		T11	11
valid_sources[0x3f]	12634	1			T2	1		T11	11		T13	2
valid_sources[0x40]	11040	1			T1	6		T2	15		T3	7
valid_sources[0x41]	162923	1			T1	2		T2	5		T3	6
valid_sources[0x42]	10505	1			T1	4		T2	7		T11	9
valid_sources[0x43]	13472	1			T1	1		T2	6		T3	6
valid_sources[0x44]	11874	1			T1	2		T2	2		T3	8
valid_sources[0x45]	10642	1			T1	2		T2	2		T11	4
valid_sources[0x46]	12122	1			T1	6		T2	1		T3	4
valid_sources[0x47]	12033	1			T1	4		T2	5		T3	5
valid_sources[0x48]	11489	1			T1	1		T2	34		T11	10
valid_sources[0x49]	11738	1			T1	3		T11	8		T13	1
valid_sources[0x4a]	10054	1			T1	2		T2	7		T3	13
valid_sources[0x4b]	12719	1			T1	2		T2	13		T3	1
valid_sources[0x4c]	11469	1			T1	1		T2	6		T11	7
valid_sources[0x4d]	10475	1			T1	4		T2	19		T11	5
valid_sources[0x4e]	10724	1			T1	1		T2	4		T11	11
valid_sources[0x4f]	16714	1			T2	6		T11	4		T13	4
valid_sources[0x50]	10291	1			T1	3		T3	4		T11	5
valid_sources[0x51]	11448	1			T1	1		T2	1		T3	2
valid_sources[0x52]	11399	1			T1	1		T2	4		T3	3
valid_sources[0x53]	12822	1			T2	4		T4	773		T11	14
valid_sources[0x54]	14452	1			T1	3		T2	14		T11	5
valid_sources[0x55]	11341	1			T2	7		T3	7		T11	6
valid_sources[0x56]	10128	1			T1	5		T2	7		T11	6
valid_sources[0x57]	10865	1			T1	2		T2	3		T11	9
valid_sources[0x58]	10717	1			T1	3		T2	17		T11	10
valid_sources[0x59]	11105	1			T1	1		T3	15		T11	10
valid_sources[0x5a]	10905	1			T1	5		T2	15		T3	20
valid_sources[0x5b]	11405	1			T1	1		T2	2		T3	12
valid_sources[0x5c]	10317	1			T1	4		T2	7		T3	11
valid_sources[0x5d]	10988	1			T2	17		T3	7		T11	8
valid_sources[0x5e]	10857	1			T1	6		T2	14		T11	10
valid_sources[0x5f]	14555	1			T1	6		T2	4		T11	9
valid_sources[0x60]	11797	1			T2	6		T3	3		T11	10
valid_sources[0x61]	10631	1			T1	2		T2	5		T3	6
valid_sources[0x62]	11166	1			T1	1		T2	3		T3	2
valid_sources[0x63]	11811	1			T1	3		T3	3		T11	7
valid_sources[0x64]	10907	1			T1	1		T2	18		T3	2
valid_sources[0x65]	12844	1			T11	10		T13	1		T33	2
valid_sources[0x66]	13235	1			T1	2		T2	1		T11	9
valid_sources[0x67]	14604	1			T1	3		T2	1		T3	15
valid_sources[0x68]	10543	1			T1	1		T2	11		T3	5
valid_sources[0x69]	11297	1			T1	4		T2	2		T3	3
valid_sources[0x6a]	11203	1			T1	3		T2	2		T3	1
valid_sources[0x6b]	11529	1			T1	3		T2	1		T11	10
valid_sources[0x6c]	10268	1			T2	4		T3	1		T11	8
valid_sources[0x6d]	10058	1			T1	4		T2	12		T11	10
valid_sources[0x6e]	11713	1			T1	1		T2	1		T11	7
valid_sources[0x6f]	10865	1			T2	2		T11	5		T13	2
valid_sources[0x70]	12881	1			T1	6		T2	3		T3	6
valid_sources[0x71]	11658	1			T1	5		T2	5		T11	12
valid_sources[0x72]	10707	1			T1	5		T2	8		T3	2
valid_sources[0x73]	11283	1			T1	1		T11	8		T13	3
valid_sources[0x74]	12338	1			T1	3		T2	5		T11	17
valid_sources[0x75]	10007	1			T2	4		T11	13		T14	6
valid_sources[0x76]	11401	1			T1	6		T2	3		T3	8
valid_sources[0x77]	11595	1			T1	2		T2	10		T11	7
valid_sources[0x78]	10993	1			T1	4		T2	6		T3	10
valid_sources[0x79]	11126	1			T1	6		T2	5		T11	11
valid_sources[0x7a]	10766	1			T1	3		T2	3		T11	11
valid_sources[0x7b]	11233	1			T1	3		T2	52		T11	11
valid_sources[0x7c]	13677	1			T1	2		T3	7		T11	11
valid_sources[0x7d]	9910	1			T1	3		T11	2		T14	13
valid_sources[0x7e]	10729	1			T1	3		T2	3		T11	7
valid_sources[0x7f]	13851	1			T1	5		T2	3		T3	1
valid_sources[0x80]	10569	1			T1	1		T2	18		T11	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

342228

1

T1

133

T2

564

T3

165

values[0x0]

all_enables

biggest_size

154592

1

T1

15

T2

81

T3

120

values[0x1]

all_enables

biggest_size

139237

1

T1

9

T2

81

T3

130