SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_sideload_ctrl.u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[0].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[1].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[2].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[3].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[4].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[5].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[6].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[7].u_mubi_buf | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | u_sideload_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 7956 | 7956 | 0 | 0 |
OutputsKnown_A | 178671951 | 177258708 | 0 | 0 |
gen_no_flops.OutputDelay_A | 178671951 | 177258708 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 7956 | 7956 | 0 | 0 |
T1 | 9 | 9 | 0 | 0 |
T2 | 9 | 9 | 0 | 0 |
T3 | 9 | 9 | 0 | 0 |
T4 | 9 | 9 | 0 | 0 |
T11 | 9 | 9 | 0 | 0 |
T12 | 9 | 9 | 0 | 0 |
T13 | 9 | 9 | 0 | 0 |
T14 | 9 | 9 | 0 | 0 |
T15 | 9 | 9 | 0 | 0 |
T16 | 9 | 9 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 178671951 | 177258708 | 0 | 0 |
T1 | 27549 | 27045 | 0 | 0 |
T2 | 55755 | 55035 | 0 | 0 |
T3 | 75078 | 74313 | 0 | 0 |
T4 | 63819 | 63243 | 0 | 0 |
T11 | 214614 | 214119 | 0 | 0 |
T12 | 10521 | 9927 | 0 | 0 |
T13 | 60408 | 59724 | 0 | 0 |
T14 | 49419 | 48564 | 0 | 0 |
T15 | 32994 | 32112 | 0 | 0 |
T16 | 38610 | 38115 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 178671951 | 177258708 | 0 | 0 |
T1 | 27549 | 27045 | 0 | 0 |
T2 | 55755 | 55035 | 0 | 0 |
T3 | 75078 | 74313 | 0 | 0 |
T4 | 63819 | 63243 | 0 | 0 |
T11 | 214614 | 214119 | 0 | 0 |
T12 | 10521 | 9927 | 0 | 0 |
T13 | 60408 | 59724 | 0 | 0 |
T14 | 49419 | 48564 | 0 | 0 |
T15 | 32994 | 32112 | 0 | 0 |
T16 | 38610 | 38115 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 884 | 884 | 0 | 0 |
OutputsKnown_A | 19852439 | 19695412 | 0 | 0 |
gen_no_flops.OutputDelay_A | 19852439 | 19695412 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 884 | 884 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 884 | 884 | 0 | 0 |
OutputsKnown_A | 19852439 | 19695412 | 0 | 0 |
gen_no_flops.OutputDelay_A | 19852439 | 19695412 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 884 | 884 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 884 | 884 | 0 | 0 |
OutputsKnown_A | 19852439 | 19695412 | 0 | 0 |
gen_no_flops.OutputDelay_A | 19852439 | 19695412 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 884 | 884 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 884 | 884 | 0 | 0 |
OutputsKnown_A | 19852439 | 19695412 | 0 | 0 |
gen_no_flops.OutputDelay_A | 19852439 | 19695412 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 884 | 884 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 884 | 884 | 0 | 0 |
OutputsKnown_A | 19852439 | 19695412 | 0 | 0 |
gen_no_flops.OutputDelay_A | 19852439 | 19695412 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 884 | 884 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 884 | 884 | 0 | 0 |
OutputsKnown_A | 19852439 | 19695412 | 0 | 0 |
gen_no_flops.OutputDelay_A | 19852439 | 19695412 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 884 | 884 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 884 | 884 | 0 | 0 |
OutputsKnown_A | 19852439 | 19695412 | 0 | 0 |
gen_no_flops.OutputDelay_A | 19852439 | 19695412 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 884 | 884 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 884 | 884 | 0 | 0 |
OutputsKnown_A | 19852439 | 19695412 | 0 | 0 |
gen_no_flops.OutputDelay_A | 19852439 | 19695412 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 884 | 884 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 884 | 884 | 0 | 0 |
OutputsKnown_A | 19852439 | 19695412 | 0 | 0 |
gen_no_flops.OutputDelay_A | 19852439 | 19695412 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 884 | 884 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19852439 | 19695412 | 0 | 0 |
T1 | 3061 | 3005 | 0 | 0 |
T2 | 6195 | 6115 | 0 | 0 |
T3 | 8342 | 8257 | 0 | 0 |
T4 | 7091 | 7027 | 0 | 0 |
T11 | 23846 | 23791 | 0 | 0 |
T12 | 1169 | 1103 | 0 | 0 |
T13 | 6712 | 6636 | 0 | 0 |
T14 | 5491 | 5396 | 0 | 0 |
T15 | 3666 | 3568 | 0 | 0 |
T16 | 4290 | 4235 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |