Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
19852439 |
19695412 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19852439 |
19695412 |
0 |
0 |
T1 |
3061 |
3005 |
0 |
0 |
T2 |
6195 |
6115 |
0 |
0 |
T3 |
8342 |
8257 |
0 |
0 |
T4 |
7091 |
7027 |
0 |
0 |
T11 |
23846 |
23791 |
0 |
0 |
T12 |
1169 |
1103 |
0 |
0 |
T13 |
6712 |
6636 |
0 |
0 |
T14 |
5491 |
5396 |
0 |
0 |
T15 |
3666 |
3568 |
0 |
0 |
T16 |
4290 |
4235 |
0 |
0 |