Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	21547171	21664	0	0
attest_sw_binding_0_rd_A	21547171	2454	0	0
attest_sw_binding_1_rd_A	21547171	2641	0	0
attest_sw_binding_2_rd_A	21547171	2394	0	0
attest_sw_binding_3_rd_A	21547171	2372	0	0
attest_sw_binding_4_rd_A	21547171	2253	0	0
attest_sw_binding_5_rd_A	21547171	2521	0	0
attest_sw_binding_6_rd_A	21547171	2572	0	0
attest_sw_binding_7_rd_A	21547171	2395	0	0
intr_enable_rd_A	21547171	3064	0	0
key_version_rd_A	21547171	2365	0	0
max_creator_key_ver_regwen_rd_A	21547171	2443	0	0
max_owner_int_key_ver_regwen_rd_A	21547171	2395	0	0
max_owner_key_ver_regwen_rd_A	21547171	2486	0	0
reseed_interval_regwen_rd_A	21547171	2514	0	0
salt_0_rd_A	21547171	2446	0	0
salt_1_rd_A	21547171	2487	0	0
salt_2_rd_A	21547171	2325	0	0
salt_3_rd_A	21547171	2292	0	0
salt_4_rd_A	21547171	2378	0	0
salt_5_rd_A	21547171	2265	0	0
salt_6_rd_A	21547171	2418	0	0
salt_7_rd_A	21547171	2467	0	0
sealing_sw_binding_0_rd_A	21547171	2337	0	0
sealing_sw_binding_1_rd_A	21547171	2469	0	0
sealing_sw_binding_2_rd_A	21547171	2383	0	0
sealing_sw_binding_3_rd_A	21547171	2398	0	0
sealing_sw_binding_4_rd_A	21547171	2372	0	0
sealing_sw_binding_5_rd_A	21547171	2345	0	0
sealing_sw_binding_6_rd_A	21547171	2285	0	0
sealing_sw_binding_7_rd_A	21547171	2418	0	0
sideload_clear_rd_A	21547171	2519	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	21664	0	0
T6	26101	435	0	0
T7	0	860	0	0
T25	2397	0	0	0
T34	13368	0	0	0
T35	1667	0	0	0
T46	117055	0	0	0
T68	0	228	0	0
T76	3005	0	0	0
T77	8064	0	0	0
T78	7577	0	0	0
T92	0	28	0	0
T105	0	298	0	0
T111	0	632	0	0
T112	0	453	0	0
T113	0	23	0	0
T114	0	194	0	0
T115	0	529	0	0
T116	42667	0	0	0
T117	10156	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2454	0	0
T70	6565	0	0	0
T109	0	27	0	0
T110	0	19	0	0
T113	23094	30	0	0
T132	0	35	0	0
T139	12392	0	0	0
T149	0	11	0	0
T163	0	71	0	0
T166	0	23	0	0
T167	0	20	0	0
T168	0	31	0	0
T169	0	27	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2641	0	0
T70	6565	0	0	0
T109	0	10	0	0
T110	0	14	0	0
T113	23094	41	0	0
T132	0	31	0	0
T133	0	7	0	0
T139	12392	0	0	0
T149	0	8	0	0
T163	0	69	0	0
T166	0	20	0	0
T167	0	11	0	0
T168	0	21	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2394	0	0
T70	6565	0	0	0
T109	0	30	0	0
T110	0	31	0	0
T113	23094	31	0	0
T132	0	7	0	0
T133	0	12	0	0
T139	12392	0	0	0
T149	0	22	0	0
T163	0	67	0	0
T166	0	26	0	0
T167	0	16	0	0
T168	0	20	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2372	0	0
T70	6565	0	0	0
T109	0	16	0	0
T110	0	16	0	0
T113	23094	21	0	0
T132	0	9	0	0
T133	0	16	0	0
T139	12392	0	0	0
T149	0	6	0	0
T163	0	81	0	0
T166	0	12	0	0
T167	0	14	0	0
T168	0	25	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2253	0	0
T70	6565	0	0	0
T109	0	12	0	0
T110	0	18	0	0
T113	23094	51	0	0
T132	0	21	0	0
T133	0	16	0	0
T139	12392	0	0	0
T149	0	5	0	0
T163	0	58	0	0
T166	0	14	0	0
T167	0	23	0	0
T168	0	38	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2521	0	0
T70	6565	0	0	0
T109	0	11	0	0
T110	0	52	0	0
T113	23094	25	0	0
T132	0	13	0	0
T133	0	7	0	0
T139	12392	0	0	0
T149	0	8	0	0
T163	0	87	0	0
T166	0	32	0	0
T167	0	23	0	0
T168	0	32	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2572	0	0
T70	6565	0	0	0
T109	0	19	0	0
T110	0	19	0	0
T113	23094	45	0	0
T132	0	15	0	0
T133	0	6	0	0
T139	12392	0	0	0
T149	0	7	0	0
T163	0	81	0	0
T166	0	22	0	0
T167	0	43	0	0
T168	0	35	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2395	0	0
T70	6565	0	0	0
T109	0	18	0	0
T110	0	13	0	0
T113	23094	26	0	0
T132	0	49	0	0
T133	0	13	0	0
T139	12392	0	0	0
T149	0	7	0	0
T163	0	89	0	0
T166	0	21	0	0
T167	0	5	0	0
T168	0	29	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	3064	0	0
T39	4127	0	0	0
T46	117055	13	0	0
T73	0	70	0	0
T90	1086	0	0	0
T92	18913	0	0	0
T113	0	57	0	0
T117	10156	0	0	0
T166	0	41	0	0
T167	0	23	0	0
T177	0	3	0	0
T178	0	21	0	0
T179	0	47	0	0
T180	0	10	0	0
T181	0	3	0	0
T182	20447	0	0	0
T183	18575	0	0	0
T184	5919	0	0	0
T185	6483	0	0	0
T186	3587	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2365	0	0
T70	6565	0	0	0
T109	0	17	0	0
T110	0	11	0	0
T113	23094	12	0	0
T132	0	24	0	0
T133	0	15	0	0
T139	12392	0	0	0
T149	0	8	0	0
T163	0	101	0	0
T166	0	33	0	0
T167	0	3	0	0
T168	0	6	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2443	0	0
T70	6565	0	0	0
T109	0	17	0	0
T110	0	28	0	0
T113	23094	22	0	0
T132	0	50	0	0
T133	0	8	0	0
T139	12392	0	0	0
T149	0	1	0	0
T163	0	87	0	0
T166	0	21	0	0
T167	0	18	0	0
T168	0	28	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2395	0	0
T70	6565	0	0	0
T109	0	17	0	0
T110	0	19	0	0
T113	23094	12	0	0
T132	0	13	0	0
T133	0	11	0	0
T139	12392	0	0	0
T149	0	20	0	0
T163	0	83	0	0
T166	0	25	0	0
T167	0	9	0	0
T168	0	32	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2486	0	0
T70	6565	0	0	0
T109	0	11	0	0
T110	0	31	0	0
T113	23094	21	0	0
T132	0	23	0	0
T133	0	11	0	0
T139	12392	0	0	0
T149	0	5	0	0
T163	0	106	0	0
T166	0	30	0	0
T167	0	25	0	0
T168	0	16	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2514	0	0
T70	6565	0	0	0
T109	0	23	0	0
T110	0	25	0	0
T113	23094	35	0	0
T132	0	54	0	0
T133	0	6	0	0
T139	12392	0	0	0
T149	0	18	0	0
T163	0	76	0	0
T166	0	32	0	0
T167	0	9	0	0
T168	0	16	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2446	0	0
T70	6565	0	0	0
T109	0	19	0	0
T110	0	51	0	0
T113	23094	26	0	0
T132	0	5	0	0
T133	0	15	0	0
T139	12392	0	0	0
T149	0	4	0	0
T163	0	85	0	0
T166	0	42	0	0
T167	0	9	0	0
T168	0	38	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2487	0	0
T70	6565	0	0	0
T109	0	10	0	0
T110	0	21	0	0
T113	23094	29	0	0
T132	0	35	0	0
T133	0	18	0	0
T139	12392	0	0	0
T149	0	17	0	0
T163	0	68	0	0
T166	0	27	0	0
T167	0	20	0	0
T168	0	30	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2325	0	0
T70	6565	0	0	0
T109	0	6	0	0
T110	0	38	0	0
T113	23094	40	0	0
T132	0	31	0	0
T133	0	1	0	0
T139	12392	0	0	0
T149	0	8	0	0
T163	0	53	0	0
T166	0	32	0	0
T167	0	21	0	0
T168	0	24	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2292	0	0
T70	6565	0	0	0
T109	0	9	0	0
T110	0	55	0	0
T113	23094	23	0	0
T132	0	17	0	0
T133	0	19	0	0
T139	12392	0	0	0
T149	0	2	0	0
T163	0	80	0	0
T166	0	13	0	0
T167	0	22	0	0
T168	0	26	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2378	0	0
T70	6565	0	0	0
T109	0	29	0	0
T110	0	16	0	0
T113	23094	12	0	0
T132	0	27	0	0
T133	0	3	0	0
T139	12392	0	0	0
T149	0	5	0	0
T163	0	75	0	0
T166	0	21	0	0
T167	0	27	0	0
T168	0	29	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2265	0	0
T70	6565	0	0	0
T109	0	23	0	0
T110	0	26	0	0
T113	23094	24	0	0
T132	0	18	0	0
T133	0	6	0	0
T139	12392	0	0	0
T149	0	11	0	0
T163	0	67	0	0
T166	0	28	0	0
T167	0	30	0	0
T168	0	26	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2418	0	0
T70	6565	0	0	0
T109	0	19	0	0
T110	0	47	0	0
T113	23094	36	0	0
T132	0	18	0	0
T133	0	6	0	0
T139	12392	0	0	0
T149	0	16	0	0
T163	0	78	0	0
T166	0	16	0	0
T167	0	16	0	0
T168	0	16	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2467	0	0
T70	6565	0	0	0
T109	0	19	0	0
T110	0	17	0	0
T113	23094	37	0	0
T132	0	60	0	0
T133	0	10	0	0
T139	12392	0	0	0
T149	0	14	0	0
T163	0	88	0	0
T166	0	21	0	0
T167	0	19	0	0
T168	0	15	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2337	0	0
T70	6565	0	0	0
T109	0	6	0	0
T113	23094	28	0	0
T132	0	42	0	0
T133	0	2	0	0
T139	12392	0	0	0
T149	0	5	0	0
T163	0	80	0	0
T166	0	10	0	0
T167	0	8	0	0
T168	0	34	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0
T187	0	2	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2469	0	0
T70	6565	0	0	0
T109	0	9	0	0
T110	0	23	0	0
T113	23094	31	0	0
T132	0	4	0	0
T133	0	11	0	0
T139	12392	0	0	0
T163	0	82	0	0
T166	0	31	0	0
T167	0	11	0	0
T168	0	25	0	0
T169	0	14	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2383	0	0
T70	6565	0	0	0
T109	0	14	0	0
T110	0	23	0	0
T113	23094	14	0	0
T132	0	17	0	0
T133	0	30	0	0
T139	12392	0	0	0
T149	0	16	0	0
T163	0	81	0	0
T166	0	32	0	0
T167	0	31	0	0
T168	0	23	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2398	0	0
T70	6565	0	0	0
T109	0	23	0	0
T110	0	31	0	0
T113	23094	34	0	0
T133	0	4	0	0
T139	12392	0	0	0
T149	0	6	0	0
T163	0	81	0	0
T166	0	28	0	0
T167	0	1	0	0
T168	0	44	0	0
T169	0	10	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2372	0	0
T70	6565	0	0	0
T109	0	15	0	0
T110	0	20	0	0
T113	23094	25	0	0
T132	0	30	0	0
T133	0	13	0	0
T139	12392	0	0	0
T149	0	8	0	0
T163	0	88	0	0
T166	0	30	0	0
T167	0	11	0	0
T168	0	18	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2345	0	0
T70	6565	0	0	0
T109	0	13	0	0
T110	0	30	0	0
T113	23094	21	0	0
T132	0	27	0	0
T133	0	13	0	0
T139	12392	0	0	0
T149	0	9	0	0
T163	0	73	0	0
T166	0	26	0	0
T167	0	19	0	0
T168	0	32	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2285	0	0
T70	6565	0	0	0
T109	0	25	0	0
T110	0	42	0	0
T113	23094	56	0	0
T132	0	24	0	0
T133	0	15	0	0
T139	12392	0	0	0
T149	0	12	0	0
T163	0	60	0	0
T166	0	33	0	0
T167	0	10	0	0
T168	0	34	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2418	0	0
T70	6565	0	0	0
T109	0	15	0	0
T110	0	32	0	0
T113	23094	20	0	0
T132	0	20	0	0
T133	0	14	0	0
T139	12392	0	0	0
T149	0	4	0	0
T163	0	73	0	0
T166	0	14	0	0
T167	0	21	0	0
T168	0	33	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21547171	2519	0	0
T70	6565	0	0	0
T109	0	28	0	0
T110	0	30	0	0
T113	23094	35	0	0
T132	0	30	0	0
T133	0	11	0	0
T139	12392	0	0	0
T149	0	15	0	0
T163	0	82	0	0
T166	0	45	0	0
T167	0	20	0	0
T168	0	32	0	0
T170	17591	0	0	0
T171	2274	0	0	0
T172	3666	0	0	0
T173	1534	0	0	0
T174	2992	0	0	0
T175	238758	0	0	0
T176	49809	0	0	0