Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3637893	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

601907

1

T1

128

T2

495

T3

149

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3825395	1			T1	1513		T2	23312		T3	407
values[0x0]	205619	1			T1	38		T2	206		T3	38
values[0x1]	208786	1			T1	52		T2	169		T3	47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2482043	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1757757

1

T1

626

T2

8064

T3

232

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13914	1			T1	3		T2	108		T3	1
valid_sources[0x01]	16235	1			T1	15		T2	75		T12	3
valid_sources[0x02]	14940	1			T1	4		T2	65		T3	1
valid_sources[0x03]	11451	1			T1	8		T2	89		T4	3
valid_sources[0x04]	12435	1			T1	3		T2	87		T3	8
valid_sources[0x05]	707158	1			T1	6		T2	96		T14	3
valid_sources[0x06]	13904	1			T1	6		T2	100		T4	2
valid_sources[0x07]	11477	1			T1	7		T2	74		T4	1
valid_sources[0x08]	13501	1			T1	4		T2	120		T12	1
valid_sources[0x09]	11966	1			T1	4		T2	84		T4	4
valid_sources[0x0a]	12583	1			T1	13		T2	87		T12	1
valid_sources[0x0b]	11161	1			T1	7		T2	93		T3	5
valid_sources[0x0c]	11176	1			T1	1		T2	88		T4	2
valid_sources[0x0d]	11133	1			T1	5		T2	98		T4	2
valid_sources[0x0e]	12290	1			T1	12		T2	104		T4	1
valid_sources[0x0f]	12465	1			T1	2		T2	90		T4	1
valid_sources[0x10]	10949	1			T1	6		T2	100		T4	2
valid_sources[0x11]	12458	1			T1	10		T2	76		T3	9
valid_sources[0x12]	11262	1			T1	1		T2	71		T4	1
valid_sources[0x13]	14043	1			T1	9		T2	99		T12	2
valid_sources[0x14]	11141	1			T1	9		T2	91		T4	1
valid_sources[0x15]	11640	1			T1	2		T2	98		T4	2
valid_sources[0x16]	12691	1			T1	4		T2	89		T4	1
valid_sources[0x17]	11187	1			T1	9		T2	82		T3	8
valid_sources[0x18]	13660	1			T1	6		T2	86		T12	2
valid_sources[0x19]	11516	1			T1	3		T2	94		T3	5
valid_sources[0x1a]	12079	1			T1	8		T2	111		T4	3
valid_sources[0x1b]	14256	1			T2	104		T12	1		T14	7
valid_sources[0x1c]	14799	1			T1	9		T2	86		T14	2
valid_sources[0x1d]	14092	1			T1	1		T2	101		T3	2
valid_sources[0x1e]	11610	1			T1	14		T2	72		T4	1
valid_sources[0x1f]	11290	1			T1	5		T2	88		T4	2
valid_sources[0x20]	11737	1			T1	4		T2	102		T12	22
valid_sources[0x21]	14076	1			T1	5		T2	99		T12	9
valid_sources[0x22]	14082	1			T1	4		T2	97		T4	1
valid_sources[0x23]	11971	1			T1	5		T2	94		T12	9
valid_sources[0x24]	11363	1			T1	8		T2	86		T3	11
valid_sources[0x25]	11428	1			T1	5		T2	70		T3	19
valid_sources[0x26]	11078	1			T1	6		T2	85		T4	1
valid_sources[0x27]	11068	1			T1	11		T2	71		T4	1
valid_sources[0x28]	12029	1			T1	13		T2	94		T4	2
valid_sources[0x29]	11234	1			T1	12		T2	80		T16	74
valid_sources[0x2a]	12729	1			T1	4		T2	70		T3	1
valid_sources[0x2b]	12338	1			T1	3		T2	77		T4	2
valid_sources[0x2c]	11558	1			T1	1		T2	89		T3	7
valid_sources[0x2d]	19091	1			T1	5		T2	91		T4	1
valid_sources[0x2e]	11281	1			T1	5		T2	92		T4	1
valid_sources[0x2f]	11000	1			T1	4		T2	92		T4	1
valid_sources[0x30]	11900	1			T1	14		T2	86		T4	1
valid_sources[0x31]	11064	1			T1	1		T2	109		T4	1
valid_sources[0x32]	11473	1			T1	5		T2	93		T3	12
valid_sources[0x33]	10731	1			T1	3		T2	83		T3	16
valid_sources[0x34]	11990	1			T1	15		T2	109		T4	1
valid_sources[0x35]	12550	1			T1	6		T2	101		T14	2
valid_sources[0x36]	11252	1			T2	92		T12	2		T14	7
valid_sources[0x37]	14037	1			T1	2		T2	102		T12	1
valid_sources[0x38]	11119	1			T1	8		T2	104		T4	1
valid_sources[0x39]	14986	1			T1	6		T2	85		T4	1
valid_sources[0x3a]	11391	1			T1	5		T2	93		T14	3
valid_sources[0x3b]	11529	1			T1	6		T2	90		T4	1
valid_sources[0x3c]	13398	1			T1	2		T2	81		T3	9
valid_sources[0x3d]	11216	1			T1	11		T2	99		T4	1
valid_sources[0x3e]	10849	1			T1	17		T2	106		T3	3
valid_sources[0x3f]	17794	1			T1	13		T2	77		T4	1
valid_sources[0x40]	13637	1			T1	22		T2	92		T4	1
valid_sources[0x41]	11176	1			T1	10		T2	94		T3	5
valid_sources[0x42]	11607	1			T1	6		T2	97		T3	2
valid_sources[0x43]	24598	1			T1	15		T2	86		T3	1
valid_sources[0x44]	12756	1			T1	7		T2	100		T4	1
valid_sources[0x45]	17044	1			T1	8		T2	80		T3	7
valid_sources[0x46]	11233	1			T1	1		T2	77		T12	13
valid_sources[0x47]	12705	1			T1	5		T2	77		T12	6
valid_sources[0x48]	11650	1			T1	11		T2	74		T4	1
valid_sources[0x49]	12175	1			T1	8		T2	118		T4	2
valid_sources[0x4a]	14452	1			T1	6		T2	74		T3	13
valid_sources[0x4b]	11979	1			T1	3		T2	90		T12	4
valid_sources[0x4c]	13230	1			T1	3		T2	90		T12	5
valid_sources[0x4d]	11363	1			T1	6		T2	78		T3	15
valid_sources[0x4e]	12044	1			T1	3		T2	95		T3	5
valid_sources[0x4f]	14285	1			T1	9		T2	92		T4	3
valid_sources[0x50]	11721	1			T1	5		T2	90		T4	1
valid_sources[0x51]	11716	1			T1	10		T2	100		T14	2
valid_sources[0x52]	11251	1			T1	12		T2	72		T14	2
valid_sources[0x53]	10923	1			T1	2		T2	102		T14	1
valid_sources[0x54]	55326	1			T1	6		T2	93		T4	1
valid_sources[0x55]	12019	1			T1	8		T2	81		T12	1
valid_sources[0x56]	13901	1			T1	4		T2	95		T3	1
valid_sources[0x57]	11125	1			T1	1		T2	99		T4	1
valid_sources[0x58]	40790	1			T1	2		T2	85		T4	1
valid_sources[0x59]	24894	1			T1	9		T2	98		T4	2
valid_sources[0x5a]	12700	1			T1	8		T2	106		T4	1
valid_sources[0x5b]	13460	1			T1	2		T2	118		T4	2
valid_sources[0x5c]	16644	1			T1	1		T2	93		T12	6
valid_sources[0x5d]	17691	1			T1	13		T2	116		T4	1
valid_sources[0x5e]	11990	1			T1	6		T2	94		T3	6
valid_sources[0x5f]	15477	1			T1	13		T2	96		T4	1
valid_sources[0x60]	11109	1			T1	6		T2	60		T4	1
valid_sources[0x61]	15459	1			T1	1		T2	95		T4	2
valid_sources[0x62]	16018	1			T1	9		T2	86		T3	16
valid_sources[0x63]	11376	1			T1	12		T2	92		T3	1
valid_sources[0x64]	14073	1			T1	11		T2	94		T4	2
valid_sources[0x65]	13992	1			T1	2		T2	88		T3	4
valid_sources[0x66]	11384	1			T1	8		T2	84		T12	8
valid_sources[0x67]	23124	1			T1	6		T2	91		T4	1
valid_sources[0x68]	11628	1			T1	6		T2	94		T3	1
valid_sources[0x69]	13865	1			T1	12		T2	78		T3	3
valid_sources[0x6a]	20161	1			T1	3		T2	84		T3	6
valid_sources[0x6b]	10872	1			T1	4		T2	82		T12	10
valid_sources[0x6c]	13159	1			T1	8		T2	96		T4	2
valid_sources[0x6d]	14145	1			T1	9		T2	85		T4	1
valid_sources[0x6e]	11538	1			T1	4		T2	97		T4	5
valid_sources[0x6f]	12790	1			T1	13		T2	101		T4	3
valid_sources[0x70]	12229	1			T1	11		T2	91		T12	1
valid_sources[0x71]	12894	1			T1	3		T2	90		T3	5
valid_sources[0x72]	19313	1			T1	2		T2	87		T12	2
valid_sources[0x73]	14582	1			T1	7		T2	83		T12	2
valid_sources[0x74]	12109	1			T1	10		T2	117		T12	1
valid_sources[0x75]	11391	1			T1	9		T2	93		T14	3
valid_sources[0x76]	23192	1			T1	10		T2	90		T3	4
valid_sources[0x77]	11994	1			T1	8		T2	85		T3	6
valid_sources[0x78]	14741	1			T1	1		T2	88		T12	3
valid_sources[0x79]	11524	1			T1	12		T2	83		T12	1
valid_sources[0x7a]	24386	1			T1	1		T2	103		T3	10
valid_sources[0x7b]	22683	1			T1	2		T2	79		T3	7
valid_sources[0x7c]	16374	1			T1	2		T2	92		T3	1
valid_sources[0x7d]	12448	1			T1	4		T2	103		T3	5
valid_sources[0x7e]	19591	1			T1	6		T2	109		T14	14
valid_sources[0x7f]	12834	1			T1	17		T2	89		T12	5
valid_sources[0x80]	11859	1			T1	6		T2	93		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

320182

1

T1

105

T2

217

T3

122

values[0x0]

all_enables

biggest_size

148361

1

T1

17

T2

155

T3

15

values[0x1]

all_enables

biggest_size

133364

1

T1

6

T2

123

T3

12