Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
22770480 |
22594658 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22770480 |
22594658 |
0 |
0 |
T1 |
5151 |
5027 |
0 |
0 |
T2 |
95147 |
95086 |
0 |
0 |
T3 |
4507 |
4421 |
0 |
0 |
T4 |
2788 |
2734 |
0 |
0 |
T12 |
2516 |
2459 |
0 |
0 |
T13 |
6155 |
6074 |
0 |
0 |
T14 |
3053 |
2980 |
0 |
0 |
T15 |
5248 |
5193 |
0 |
0 |
T16 |
75014 |
74947 |
0 |
0 |
T17 |
2773 |
2676 |
0 |
0 |