Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24490888	16827	0	0
attest_sw_binding_0_rd_A	24490888	2956	0	0
attest_sw_binding_1_rd_A	24490888	3073	0	0
attest_sw_binding_2_rd_A	24490888	3164	0	0
attest_sw_binding_3_rd_A	24490888	2995	0	0
attest_sw_binding_4_rd_A	24490888	3177	0	0
attest_sw_binding_5_rd_A	24490888	3034	0	0
attest_sw_binding_6_rd_A	24490888	3077	0	0
attest_sw_binding_7_rd_A	24490888	3157	0	0
intr_enable_rd_A	24490888	3756	0	0
key_version_rd_A	24490888	2972	0	0
max_creator_key_ver_regwen_rd_A	24490888	2940	0	0
max_owner_int_key_ver_regwen_rd_A	24490888	3188	0	0
max_owner_key_ver_regwen_rd_A	24490888	3144	0	0
reseed_interval_regwen_rd_A	24490888	2880	0	0
salt_0_rd_A	24490888	3204	0	0
salt_1_rd_A	24490888	3089	0	0
salt_2_rd_A	24490888	3088	0	0
salt_3_rd_A	24490888	3077	0	0
salt_4_rd_A	24490888	3098	0	0
salt_5_rd_A	24490888	3033	0	0
salt_6_rd_A	24490888	2923	0	0
salt_7_rd_A	24490888	2974	0	0
sealing_sw_binding_0_rd_A	24490888	2995	0	0
sealing_sw_binding_1_rd_A	24490888	3128	0	0
sealing_sw_binding_2_rd_A	24490888	3073	0	0
sealing_sw_binding_3_rd_A	24490888	2977	0	0
sealing_sw_binding_4_rd_A	24490888	3219	0	0
sealing_sw_binding_5_rd_A	24490888	3162	0	0
sealing_sw_binding_6_rd_A	24490888	2992	0	0
sealing_sw_binding_7_rd_A	24490888	3025	0	0
sideload_clear_rd_A	24490888	3152	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	16827	0	0
T7	0	426	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	209	0	0
T58	0	828	0	0
T68	0	114	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	39	0	0
T124	0	1447	0	0
T134	0	439	0	0
T135	0	126	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T141	0	114	0	0
T142	0	44	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	2956	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	72	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	91	0	0
T173	0	5	0	0
T193	0	53	0	0
T194	0	32	0	0
T195	0	15	0	0
T196	0	18	0	0
T197	0	43	0	0
T198	0	18	0	0
T199	0	45	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3073	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	65	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	88	0	0
T173	0	5	0	0
T193	0	42	0	0
T194	0	41	0	0
T195	0	42	0	0
T196	0	29	0	0
T197	0	49	0	0
T198	0	29	0	0
T199	0	50	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3164	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	64	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	74	0	0
T173	0	3	0	0
T193	0	43	0	0
T194	0	17	0	0
T195	0	13	0	0
T196	0	31	0	0
T197	0	56	0	0
T198	0	29	0	0
T199	0	73	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	2995	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	87	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	72	0	0
T173	0	7	0	0
T193	0	48	0	0
T194	0	43	0	0
T195	0	26	0	0
T196	0	26	0	0
T197	0	71	0	0
T198	0	23	0	0
T199	0	56	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3177	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	42	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	91	0	0
T173	0	4	0	0
T193	0	62	0	0
T194	0	32	0	0
T195	0	28	0	0
T196	0	24	0	0
T197	0	47	0	0
T198	0	24	0	0
T199	0	55	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3034	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	56	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	95	0	0
T173	0	2	0	0
T193	0	63	0	0
T194	0	26	0	0
T195	0	20	0	0
T196	0	33	0	0
T197	0	54	0	0
T198	0	20	0	0
T199	0	55	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3077	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	48	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	71	0	0
T173	0	7	0	0
T193	0	47	0	0
T194	0	50	0	0
T195	0	25	0	0
T196	0	21	0	0
T197	0	72	0	0
T198	0	26	0	0
T199	0	65	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3157	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	57	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	75	0	0
T173	0	4	0	0
T193	0	51	0	0
T194	0	31	0	0
T195	0	34	0	0
T196	0	34	0	0
T197	0	63	0	0
T198	0	31	0	0
T199	0	66	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3756	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	82	0	0
T50	0	27	0	0
T72	42654	0	0	0
T75	0	16	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T193	0	55	0	0
T194	0	84	0	0
T195	0	49	0	0
T200	0	63	0	0
T201	0	7	0	0
T202	0	39	0	0
T203	0	15	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	2972	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	54	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	79	0	0
T173	0	9	0	0
T193	0	43	0	0
T194	0	15	0	0
T195	0	28	0	0
T196	0	22	0	0
T197	0	63	0	0
T198	0	18	0	0
T199	0	50	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	2940	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	50	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	78	0	0
T173	0	8	0	0
T193	0	47	0	0
T194	0	50	0	0
T195	0	21	0	0
T196	0	23	0	0
T197	0	37	0	0
T198	0	29	0	0
T199	0	36	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3188	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	73	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	74	0	0
T173	0	2	0	0
T193	0	59	0	0
T194	0	34	0	0
T195	0	24	0	0
T196	0	39	0	0
T197	0	36	0	0
T198	0	33	0	0
T199	0	53	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3144	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	67	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	65	0	0
T173	0	2	0	0
T193	0	52	0	0
T194	0	39	0	0
T195	0	15	0	0
T196	0	14	0	0
T197	0	39	0	0
T198	0	41	0	0
T199	0	52	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	2880	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	90	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	78	0	0
T173	0	5	0	0
T193	0	43	0	0
T194	0	39	0	0
T195	0	31	0	0
T196	0	13	0	0
T197	0	57	0	0
T198	0	43	0	0
T199	0	38	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3204	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	68	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T173	0	5	0	0
T193	0	48	0	0
T194	0	42	0	0
T195	0	32	0	0
T196	0	17	0	0
T197	0	44	0	0
T198	0	24	0	0
T199	0	49	0	0
T204	0	3	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3089	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	87	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	82	0	0
T173	0	1	0	0
T193	0	44	0	0
T194	0	50	0	0
T195	0	27	0	0
T196	0	26	0	0
T197	0	48	0	0
T198	0	28	0	0
T199	0	55	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3088	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	28	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	95	0	0
T173	0	1	0	0
T193	0	68	0	0
T194	0	23	0	0
T195	0	37	0	0
T196	0	39	0	0
T197	0	49	0	0
T198	0	45	0	0
T199	0	42	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3077	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	43	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	90	0	0
T173	0	3	0	0
T193	0	66	0	0
T194	0	18	0	0
T195	0	20	0	0
T196	0	22	0	0
T197	0	45	0	0
T198	0	21	0	0
T199	0	34	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3098	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	61	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	92	0	0
T173	0	1	0	0
T193	0	49	0	0
T194	0	17	0	0
T195	0	38	0	0
T196	0	33	0	0
T197	0	37	0	0
T198	0	47	0	0
T199	0	47	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3033	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	56	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	57	0	0
T173	0	5	0	0
T193	0	47	0	0
T194	0	34	0	0
T195	0	20	0	0
T196	0	23	0	0
T197	0	44	0	0
T198	0	23	0	0
T199	0	49	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	2923	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	97	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T173	0	1	0	0
T193	0	40	0	0
T194	0	13	0	0
T195	0	18	0	0
T196	0	32	0	0
T197	0	45	0	0
T198	0	26	0	0
T199	0	41	0	0
T205	0	7	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	2974	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	47	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	77	0	0
T173	0	6	0	0
T193	0	50	0	0
T194	0	31	0	0
T195	0	29	0	0
T196	0	27	0	0
T197	0	36	0	0
T198	0	23	0	0
T199	0	45	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	2995	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	54	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	97	0	0
T173	0	6	0	0
T193	0	44	0	0
T194	0	23	0	0
T195	0	52	0	0
T196	0	17	0	0
T197	0	40	0	0
T198	0	33	0	0
T199	0	50	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3128	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	91	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	86	0	0
T173	0	7	0	0
T193	0	41	0	0
T194	0	22	0	0
T195	0	39	0	0
T196	0	28	0	0
T197	0	60	0	0
T198	0	32	0	0
T199	0	65	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3073	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	55	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	75	0	0
T173	0	2	0	0
T193	0	75	0	0
T194	0	32	0	0
T195	0	29	0	0
T196	0	22	0	0
T197	0	60	0	0
T198	0	33	0	0
T199	0	59	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	2977	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	49	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	71	0	0
T173	0	1	0	0
T193	0	34	0	0
T194	0	24	0	0
T195	0	12	0	0
T196	0	18	0	0
T197	0	48	0	0
T198	0	40	0	0
T199	0	41	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3219	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	76	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	90	0	0
T173	0	10	0	0
T193	0	51	0	0
T194	0	51	0	0
T195	0	38	0	0
T196	0	13	0	0
T197	0	62	0	0
T198	0	31	0	0
T199	0	51	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3162	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	53	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	72	0	0
T173	0	7	0	0
T193	0	49	0	0
T194	0	51	0	0
T195	0	22	0	0
T196	0	53	0	0
T197	0	62	0	0
T198	0	37	0	0
T199	0	47	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	2992	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	80	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	71	0	0
T173	0	4	0	0
T193	0	34	0	0
T194	0	11	0	0
T195	0	10	0	0
T196	0	28	0	0
T197	0	29	0	0
T198	0	34	0	0
T199	0	46	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3025	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	76	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	87	0	0
T173	0	1	0	0
T193	0	56	0	0
T194	0	15	0	0
T195	0	19	0	0
T196	0	24	0	0
T197	0	29	0	0
T198	0	30	0	0
T199	0	84	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24490888	3152	0	0
T21	5198	0	0	0
T37	3841	0	0	0
T48	58239	64	0	0
T72	42654	0	0	0
T82	15174	0	0	0
T83	2927	0	0	0
T84	67157	0	0	0
T110	23414	0	0	0
T139	155900	0	0	0
T140	15202	0	0	0
T168	0	100	0	0
T173	0	5	0	0
T193	0	42	0	0
T194	0	26	0	0
T195	0	19	0	0
T196	0	24	0	0
T197	0	49	0	0
T198	0	31	0	0
T199	0	49	0	0