Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2851528	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

610475

1

T1

359

T2

302

T3

324

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3041112	1			T1	6209		T2	497		T3	776
values[0x0]	209103	1			T1	147		T2	86		T3	84
values[0x1]	211788	1			T1	155		T2	84		T3	103

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1959085	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1502918

1

T1

2392

T2

396

T3

508

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10417	1			T1	24		T2	3		T3	2
valid_sources[0x01]	12128	1			T1	17		T3	6		T16	3
valid_sources[0x02]	12614	1			T1	34		T2	2		T3	3
valid_sources[0x03]	10069	1			T1	40		T2	2		T3	8
valid_sources[0x04]	19929	1			T1	60		T2	1		T3	3
valid_sources[0x05]	10775	1			T1	40		T2	3		T3	6
valid_sources[0x06]	10352	1			T1	25		T2	7		T3	4
valid_sources[0x07]	51190	1			T1	18		T2	5		T3	1
valid_sources[0x08]	11378	1			T1	31		T2	2		T3	3
valid_sources[0x09]	10995	1			T1	25		T2	5		T3	4
valid_sources[0x0a]	12310	1			T1	7		T2	2		T3	5
valid_sources[0x0b]	10771	1			T1	29		T3	8		T4	19
valid_sources[0x0c]	12652	1			T1	32		T2	3		T3	5
valid_sources[0x0d]	10869	1			T1	11		T2	1		T3	5
valid_sources[0x0e]	10281	1			T1	27		T2	1		T3	6
valid_sources[0x0f]	11860	1			T1	25		T2	1		T3	2
valid_sources[0x10]	10648	1			T1	28		T2	5		T3	3
valid_sources[0x11]	10798	1			T1	24		T2	1		T3	3
valid_sources[0x12]	15286	1			T1	4		T2	1		T3	1
valid_sources[0x13]	10236	1			T1	20		T2	2		T3	2
valid_sources[0x14]	11155	1			T1	21		T3	3		T4	10
valid_sources[0x15]	28387	1			T1	10		T2	3		T3	5
valid_sources[0x16]	10543	1			T1	22		T2	6		T3	1
valid_sources[0x17]	71846	1			T1	38		T2	10		T3	2
valid_sources[0x18]	11148	1			T1	46		T2	3		T3	8
valid_sources[0x19]	11844	1			T1	7		T2	1		T3	3
valid_sources[0x1a]	13277	1			T1	24		T2	4		T3	1
valid_sources[0x1b]	11372	1			T1	19		T2	1		T4	10
valid_sources[0x1c]	10502	1			T1	39		T2	1		T3	6
valid_sources[0x1d]	10714	1			T1	24		T2	3		T3	4
valid_sources[0x1e]	9954	1			T1	26		T2	1		T3	4
valid_sources[0x1f]	10458	1			T1	14		T2	2		T3	4
valid_sources[0x20]	10913	1			T1	15		T2	2		T3	2
valid_sources[0x21]	10882	1			T1	50		T2	5		T3	5
valid_sources[0x22]	9974	1			T1	24		T2	1		T3	3
valid_sources[0x23]	14001	1			T1	14		T2	1		T3	3
valid_sources[0x24]	10659	1			T1	23		T2	3		T3	2
valid_sources[0x25]	16773	1			T1	20		T2	3		T3	5
valid_sources[0x26]	9847	1			T1	15		T2	1		T3	5
valid_sources[0x27]	10413	1			T1	18		T2	1		T3	4
valid_sources[0x28]	10082	1			T1	24		T2	3		T3	3
valid_sources[0x29]	13886	1			T1	23		T2	1		T3	6
valid_sources[0x2a]	24847	1			T1	5		T2	5		T3	3
valid_sources[0x2b]	18451	1			T1	20		T2	5		T3	1
valid_sources[0x2c]	11088	1			T1	24		T2	4		T3	4
valid_sources[0x2d]	11334	1			T1	24		T2	2		T3	4
valid_sources[0x2e]	11002	1			T1	37		T2	5		T3	6
valid_sources[0x2f]	11356	1			T1	19		T2	1		T3	2
valid_sources[0x30]	46880	1			T1	11		T3	1		T16	3
valid_sources[0x31]	16614	1			T1	6		T2	4		T3	1
valid_sources[0x32]	13279	1			T1	14		T2	5		T3	3
valid_sources[0x33]	9775	1			T1	18		T2	1		T3	2
valid_sources[0x34]	11876	1			T1	43		T2	3		T3	3
valid_sources[0x35]	11488	1			T1	18		T2	3		T3	2
valid_sources[0x36]	21118	1			T1	21		T2	3		T3	5
valid_sources[0x37]	11422	1			T1	53		T2	1		T3	2
valid_sources[0x38]	10174	1			T1	14		T2	7		T3	4
valid_sources[0x39]	37227	1			T1	35		T2	2		T3	5
valid_sources[0x3a]	9975	1			T1	16		T2	3		T3	6
valid_sources[0x3b]	14819	1			T1	15		T2	1		T3	3
valid_sources[0x3c]	10696	1			T1	29		T2	8		T3	1
valid_sources[0x3d]	10652	1			T1	30		T2	5		T3	3
valid_sources[0x3e]	11274	1			T1	19		T2	2		T3	5
valid_sources[0x3f]	9688	1			T1	13		T2	4		T3	5
valid_sources[0x40]	24646	1			T1	35		T2	4		T3	3
valid_sources[0x41]	10776	1			T1	17		T2	1		T3	6
valid_sources[0x42]	14333	1			T1	19		T2	3		T3	2
valid_sources[0x43]	11862	1			T1	44		T3	3		T4	1
valid_sources[0x44]	11454	1			T1	20		T3	2		T4	34
valid_sources[0x45]	9981	1			T1	48		T2	2		T3	4
valid_sources[0x46]	12097	1			T1	57		T3	5		T4	6
valid_sources[0x47]	11576	1			T1	17		T2	3		T3	3
valid_sources[0x48]	11205	1			T1	44		T2	5		T3	1
valid_sources[0x49]	16971	1			T1	37		T2	4		T3	4
valid_sources[0x4a]	10347	1			T1	39		T2	2		T3	4
valid_sources[0x4b]	11894	1			T1	16		T2	1		T3	3
valid_sources[0x4c]	11883	1			T1	32		T2	1		T3	1
valid_sources[0x4d]	11138	1			T1	18		T3	6		T4	8
valid_sources[0x4e]	17574	1			T1	36		T2	2		T3	3
valid_sources[0x4f]	10726	1			T1	14		T2	9		T3	7
valid_sources[0x50]	10452	1			T1	17		T2	1		T3	1
valid_sources[0x51]	10322	1			T1	23		T2	2		T3	4
valid_sources[0x52]	10608	1			T1	15		T2	3		T3	3
valid_sources[0x53]	15842	1			T1	16		T2	9		T3	4
valid_sources[0x54]	9603	1			T1	33		T2	2		T3	2
valid_sources[0x55]	25109	1			T1	28		T2	1		T3	6
valid_sources[0x56]	10371	1			T1	12		T2	8		T3	1
valid_sources[0x57]	9928	1			T1	30		T2	4		T4	27
valid_sources[0x58]	13314	1			T1	18		T2	2		T3	5
valid_sources[0x59]	18956	1			T1	19		T2	1		T3	4
valid_sources[0x5a]	19516	1			T1	34		T3	3		T4	3
valid_sources[0x5b]	12892	1			T1	19		T2	2		T3	6
valid_sources[0x5c]	10485	1			T1	24		T2	4		T3	4
valid_sources[0x5d]	10048	1			T1	13		T2	2		T3	1
valid_sources[0x5e]	10589	1			T1	25		T3	1		T4	31
valid_sources[0x5f]	11312	1			T1	9		T2	2		T3	5
valid_sources[0x60]	18843	1			T1	54		T2	2		T3	2
valid_sources[0x61]	10393	1			T1	23		T2	1		T3	4
valid_sources[0x62]	10583	1			T1	17		T2	2		T3	3
valid_sources[0x63]	16285	1			T1	66		T3	4		T4	2
valid_sources[0x64]	23352	1			T1	22		T2	2		T3	6
valid_sources[0x65]	12893	1			T1	26		T2	2		T3	5
valid_sources[0x66]	9901	1			T1	33		T2	2		T3	4
valid_sources[0x67]	10180	1			T1	32		T2	5		T3	9
valid_sources[0x68]	13786	1			T1	35		T2	3		T3	3
valid_sources[0x69]	28851	1			T1	27		T2	2		T3	5
valid_sources[0x6a]	10252	1			T1	16		T2	1		T3	6
valid_sources[0x6b]	10079	1			T1	14		T2	2		T3	3
valid_sources[0x6c]	10632	1			T1	37		T2	4		T4	10
valid_sources[0x6d]	12024	1			T1	8		T2	2		T16	3
valid_sources[0x6e]	10925	1			T1	42		T2	2		T3	3
valid_sources[0x6f]	10474	1			T1	22		T2	1		T3	2
valid_sources[0x70]	31934	1			T1	19		T2	4		T3	7
valid_sources[0x71]	23928	1			T1	34		T2	1		T3	4
valid_sources[0x72]	10635	1			T1	17		T2	1		T3	2
valid_sources[0x73]	42141	1			T1	56		T2	2		T3	4
valid_sources[0x74]	10481	1			T1	11		T3	4		T4	26
valid_sources[0x75]	10720	1			T1	23		T2	6		T3	5
valid_sources[0x76]	9894	1			T1	21		T2	2		T3	7
valid_sources[0x77]	13824	1			T1	24		T3	4		T4	3
valid_sources[0x78]	11985	1			T1	10		T2	4		T3	5
valid_sources[0x79]	10447	1			T1	42		T2	4		T3	2
valid_sources[0x7a]	22568	1			T1	21		T2	4		T3	6
valid_sources[0x7b]	10832	1			T1	44		T2	2		T3	1
valid_sources[0x7c]	17366	1			T1	10		T2	2		T3	5
valid_sources[0x7d]	11300	1			T1	19		T2	3		T3	1
valid_sources[0x7e]	11265	1			T1	23		T2	5		T3	2
valid_sources[0x7f]	10204	1			T1	8		T2	1		T3	4
valid_sources[0x80]	10555	1			T1	34		T2	1		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

323839

1

T1

144

T2

217

T3

186

values[0x0]

all_enables

biggest_size

150486

1

T1

108

T2

44

T3

62

values[0x1]

all_enables

biggest_size

136150

1

T1

107

T2

41

T3

76