SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
92.86 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[keymgr_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 3504227 | 0 | T1 | 6511 | T2 | 667 | T3 | 963 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3503983 | 1 | T1 | 6511 | T2 | 667 | T3 | 963 | ||||
values[1] | 24 | 1 | T386 | 1 | T166 | 4 | T167 | 1 | ||||
values[2] | 9 | 1 | T178 | 1 | T166 | 1 | T190 | 1 | ||||
values[3] | 126 | 1 | T42 | 1 | T43 | 1 | T48 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3504004 | 1 | T1 | 6511 | T2 | 667 | T3 | 963 | ||||
values[1] | 11 | 1 | T387 | 1 | T166 | 1 | T179 | 2 | ||||
values[2] | 10 | 1 | T166 | 2 | T179 | 2 | T181 | 1 | ||||
values[3] | 139 | 1 | T42 | 1 | T69 | 1 | T70 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 3503877 | 1 | T1 | 6511 | T2 | 667 | T3 | 963 | ||||
auto[TlIntgErrCmd] | 127 | 1 | T43 | 1 | T48 | 1 | T74 | 1 | ||||
auto[TlIntgErrData] | 106 | 1 | T70 | 1 | T71 | 1 | T388 | 1 | ||||
auto[TlIntgErrBoth] | 117 | 1 | T42 | 1 | T69 | 1 | T49 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |