Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
20879414 |
20710494 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20879414 |
20710494 |
0 |
0 |
T1 |
99799 |
99722 |
0 |
0 |
T2 |
6716 |
6576 |
0 |
0 |
T3 |
12990 |
12915 |
0 |
0 |
T4 |
11872 |
11728 |
0 |
0 |
T14 |
6102 |
6049 |
0 |
0 |
T15 |
129928 |
129867 |
0 |
0 |
T16 |
7892 |
7797 |
0 |
0 |
T17 |
9191 |
9109 |
0 |
0 |
T18 |
2533 |
2476 |
0 |
0 |
T19 |
9698 |
9642 |
0 |
0 |